CDC111 DRIVER Datasheet

CDC111 Datasheet, PDF, Equivalent


Part Number

CDC111

Description

1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER

Manufacture

etcTI

Total Page 12 Pages
Datasheet
Download CDC111 Datasheet


CDC111
CDC111
1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER
D Low-Output Skew for Clock-Distribution
Applications
D Differential Low-Voltage Pseudo-ECL
(LVPECL)-Compatible Inputs and Outputs
D Distributes Differential Clock Inputs to Nine
Differential Clock Outputs
D Output Reference Voltage, VREF , Allows
Distribution From a Single-Ended Clock
Input
D Single-Ended LVPECL-Compatible Output
Enable
D Packaged in Plastic Chip Carrier
description
SCAS321G – SEPTEMBER 1993 – REVISED AUGUST 1999
FN PACKAGE
(TOP VIEW)
Y8
Y8
Y7
VCC0
Y7
Y6
Y6
4 3 2 1 28 27 26
5 25
6 24
7 23
8 22
9 21
10 20
11 19
12 13 14 15 16 17 18
Y0
Y0
Y1
VCC0
Y1
Y2
Y2
The differential LVPECL clock-driver circuit
distributes one pair of differential LVPECL clock
inputs (CLKIN, CLKIN) to nine pairs of differential
clock (Y, Y) outputs with minimum skew for clock
distribution. It is specifically designed for driving
50-transmission lines.
NC – No internal connection
When the output-enable (OE) is low, the nine differential outputs switch at the same frequency as the differential
clock inputs. When OE is high, the nine differential outputs are in static states (Y outputs are in the low state,
Y outputs are in the high state).
The VREF output can be strapped to the CLKIN input for a single-ended CLKIN input.
The CDC111 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUTS
CLKIN CLKIN OE
Yn Yn
X X H LH
L H L LH
H L L HL
L
H
VREF
VREF
VREF
VREF
L
H
L
L
L
L
LH
HL
HL
LH
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1999, Texas Instruments Incorporated
1

CDC111
CDC111
1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER
SCAS321G – SEPTEMBER 1993 – REVISED AUGUST 1999
logic diagram (positive logic)
CLKIN
CLKIN
OE
28
2
27
25 Y0
24
Y0
23 Y1
21 Y1
20
Y2
19 Y2
18
Y3
17 Y3
16 Y4
14 Y4
13
Y5
12 Y5
11 Y6
10 Y6
9 Y7
7
Y7
6 Y8
5
Y8
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 4.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 18 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 18 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 50 mA
"Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 mA
Maximum power dissipation at TA = 55°C (in still air) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 mW
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a juction temperature of 150_C and a board trace length of 750 mils.
For more information, refer to the Package Thermal Considerations application note in the ABT Advanced BiCMOS Technology Data
Book, literature number SCBD002.
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Features CDC111 1-LINE TO 9-LINE DIFFERENTIAL LVP ECL CLOCK DRIVER D Low-Output Skew for Clock-Distribution Applications D Diff erential Low-Voltage Pseudo-ECL (LVPECL )-Compatible Inputs and Outputs D Distr ibutes Differential Clock Inputs to Nin e Differential Clock Outputs D Output R eference Voltage, VREF , Allows Distrib ution From a Single-Ended Clock Input D Single-Ended LVPECL-Compatible Output Enable D Packaged in Plastic Chip Carri er description SCAS321G – SEPTEMBER 1993 – REVISED AUGUST 1999 FN PACKAGE (TOP VIEW) NC VREF CLKIN V CC CLKIN O E GND Y8 Y8 Y7 VCC0 Y7 Y6 Y6 4 3 2 1 28 27 26 5 25 6 24 7 23 8 22 9 21 10 20 11 19 12 13 14 15 16 17 18 Y0 Y0 Y1 V CC0 Y1 Y2 Y2 Y5 Y5 Y4 VCC0 Y4 Y3 Y3 T he differential LVPECL clock-driver cir cuit distributes one pair of differenti al LVPECL clock inputs (CLKIN, CLKIN) t o nine pairs of differential clock (Y, Y) outputs with minimum skew for clock distribution. It is specifically design ed for driving 50-Ω transmission lines. NC – No internal connectio.
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