CDC208 Drivers Datasheet

CDC208 Datasheet, PDF, Equivalent


Part Number

CDC208

Description

Dual 1-Line To 4-Line Clock Drivers

Manufacture

etcTI

Total Page 16 Pages
Datasheet
Download CDC208 Datasheet


CDC208
ąą
D Low-Skew Propagation Delay
Specifications for Clock-Driver
Applications
D TTL-Compatible Inputs and
CMOS-Compatible Outputs
D Flow-Through Architecture Optimizes
PCB Layout
D Center-Pin VCC and GND Pin
Configurations Minimize High-Speed
Switching Noise
D EPIC (Enhanced-Performance Implanted
CMOS) 1-µm Process
D 500-mA Typical Latch-Up Immunity at
125°C
D Package Options Include Plastic
Small-Outline (DW)
CDC208
DUAL 1ĆLINE TO 4ĆLINE CLOCK DRIVER
WITH 3ĆSTATE OUTPUTS
SCAS109F − APRIL 1990 − REVISED OCTOBER 1998
DW PACKAGE
(TOP VIEW)
1Y2
1Y3
1Y4
GND
GND
GND
GND
2Y1
2Y2
2Y3
1
2
3
4
5
6
7
8
9
10
20 1Y1
19 1A
18 1OE1
17 1OE2
16 VCC
15 VCC
14 2A
13 2OE1
12 2OE2
11 2Y4
description
The CDC208 contains dual clock-driver circuits that fanout one input signal to four outputs with minimum skew
for clock distribution (see Figure 2). The device also offers two output-enable (OE1 and OE2) inputs for each
circuit that can force the outputs to be disabled to a high-impedance state or to a high- or low-logic level
independent of the signal on the respective A input.
Skew parameters are specified for a reduced temperature and voltage range common to many applications.
The CDC208 is characterized for operation from − 40°C to 85°C.
INPUTS
1OE1 1OE2
LL
LL
LH
HL
HH
FUNCTION TABLES
OUTPUTS
1A 1Y1 1Y2 1Y3
LLLL
HHHH
XLLL
XHHH
XZZZ
1Y4
L
H
L
H
Z
INPUTS
2OE1 2OE2
LL
LL
LH
HL
HH
2A
L
H
X
X
X
OUTPUTS
2Y1 2Y2 2Y3 2Y4
LLLL
HHHH
LLLL
HHHH
ZZZZ
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1998, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1

CDC208
CDC208
DUAL 1ĆLINE TO 4ĆLINE CLOCK DRIVER
WITH 3ĆSTATE OUTPUTS
SCAS109F − APRIL 1990 − REVISED OCTOBER 1998
logic symbol
18
1OE1
17
1OE2
19
1A
13
2OE1
12
2OE2
14
2A
X/Y
1
1
2
2
3
1
V4
G5
EN
4, 5
4, 5
4, 5
4, 5
20
1Y1
1
1Y2
2
1Y3
3
1Y4
8
2Y1
9
2Y2
10
2Y3
11
2Y4
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
18
1OE1
17
1OE2
1A 19
2OE1 13
12
2OE2
2A 14
ą
20
1Y1
1
1Y2
2
1Y3
3
1Y4
8
2Y1
9
2Y2
10
2Y3
11
2Y4
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Features ąą D Low-Skew Propagation Delay Specif ications for Clock-Driver Applications D TTL-Compatible Inputs and CMOS-Compat ible Outputs D Flow-Through Architectur e Optimizes PCB Layout D Center-Pin VCC and GND Pin Configurations Minimize Hi gh-Speed Switching Noise D EPIC  (En hanced-Performance Implanted CMOS) 1-µ m Process D 500-mA Typical Latch-Up Imm unity at 125°C D Package Options Inclu de Plastic Small-Outline (DW) CDC208 D UAL 1ĆLINE TO 4ĆLINE CLOCK DRIVER WIT H 3ĆSTATE OUTPUTS SCAS109F − APRIL 1 990 − REVISED OCTOBER 1998 DW PACKAGE (TOP VIEW) 1Y2 1Y3 1Y4 GND GND GND GN D 2Y1 2Y2 2Y3 1 2 3 4 5 6 7 8 9 10 20 1Y1 19 1A 18 1OE1 17 1OE2 16 VCC 15 VC C 14 2A 13 2OE1 12 2OE2 11 2Y4 descrip tion The CDC208 contains dual clock-dri ver circuits that fanout one input sign al to four outputs with minimum skew fo r clock distribution (see Figure 2). Th e device also offers two output-enable (OE1 and OE2) inputs for each circuit t hat can force the outputs to be disabled to a high-impedance state or to a h.
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