OCTAL D-TYPE FLIP-FLOP
• Contains Eight Flip-Flops With Single-Rail
Outputs
• Buffered Clock and Direct Clear Inputs • Individual Data Input to...
Description
Contains Eight Flip-Flops With Single-Rail
Outputs
Buffered Clock and Direct Clear Inputs Individual Data Input to Each Flip-Flop Applications Include:
Buffer/Storage Registers Shift Registers Pattern Generators
description
These monolithic, positive-edge-triggered flipflops utilize TTL circuitry to implement D-type flip-flop logic with a direct clear input.
Information at the D inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock input is at either the high or low level, the D input signal has no effect ar the output.
These flip-flops are guaranteed to respond to clock frequencies ranging form 0 to 30 megahertz while maximum clock frequency is typically 40 megahertz. Typical power dissipation is 39 milliwatts per flip-flop for the ′273 and 10 milliwatts for the ′LS273.
SN54273, SN54LS273, SN74273, SN74LS273 OCTAL D-TYPE FLIP-FLOP WITH CLEAR
SDLS090 – OCTOBER 1976 – REVISED MARCH 1988
SN54273, SN74LS273 . . . J OR W PACKAGE SN74273 . . . N PACKAGE
SN74LS273 . . . DW OR N PACKAGE (TOP VIEW)
CLR 1Q 1D 2D 2Q 3Q 3D 4D 4Q
GND
1 2 3 4 5 6 7 8 9 10
20 VCC 19 8Q 18 8D 17 7D 16 7Q 15 6Q 14 6D 13 5D 12 5Q 11 CLK
SN54LS273 . . . FK PACKAGE (TOP VIEW)
1D 1Q CLR V CC 8Q
2D
3 2 1 20 19 4 18
8D
2Q 5
17 7D
3Q 6
16 7Q
3D 7
15 6Q
4D 8
14 6D
9 10 11 12 1...
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