CD54ACT00 GATES Datasheet

CD54ACT00 Datasheet, PDF, Equivalent


Part Number

CD54ACT00

Description

QUADRUPLE 2-INPUT POSITIVE-NAND GATES

Manufacture

etcTI

Total Page 15 Pages
Datasheet
Download CD54ACT00 Datasheet


CD54ACT00
CD54ACT00, CD74ACT00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
D Inputs Are TTL-Voltage Compatible
D Speed of Bipolar F, AS, and S, With
Significantly Reduced Power Consumption
D Balanced Propagation Delays
D ±24-mA Output Drive Current
– Fanout to 15 F Devices
D SCR-Latchup-Resistant CMOS Process and
Circuit Design
D Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
SCHS308B – JANUARY 2001 – REVISED JUNE 2002
CD54ACT00 . . . F PACKAGE
CD74ACT00 . . . E OR M PACKAGE
(TOP VIEW)
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
14 VCC
13 4B
12 4A
11 4Y
10 3B
9 3A
8 3Y
description
The ‘ACT00 devices contain four independent 2-input NAND gates. Each gate performs the Boolean function
of Y = A S B or Y = A + B in positive logic.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – E Tube
CD74ACT00E
CD74ACT00E
Tube
–55°C to 125°C SOIC – M
Tape and reel
CD74ACT00M
CD74ACT00M96
ACT00M
CDIP – F Tube
CD54ACT00F3A CD54ACT00F3A
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
(each gate)
INPUTS
AB
OUTPUT
Y
HH
L
LX
H
XL
H
logic diagram, each gate (positive logic)
A
B
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1

CD54ACT00
CD54ACT00, CD74ACT00
QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCHS308B JANUARY 2001 REVISED JUNE 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 6 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditionsis not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
TA = 25°C
MIN MAX
40°C TO
85°C
MIN MAX
55°C TO
125°C
MIN MAX
UNIT
VCC
VIH
VIL
VI
VO
IOH
IOL
t/v
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
Output voltage
High-level output current
Low-level output current
Input transition rise or fall rate
4.5 5.5
2
0.8
0 VCC
0 VCC
24
24
10
4.5 5.5
2
0.8
0 VCC
0 VCC
24
24
10
4.5 5.5 V
2V
0.8 V
0 VCC
0 VCC
24
V
V
mA
24 mA
10 ns/V
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C
MIN MAX
40°C TO
85°C
MIN MAX
55°C TO
125°C
MIN MAX
UNIT
IOH = 50 µA
4.5 V
4.4
4.4
4.4
VOH
VI = VIH or VIL
IOH = 24 mA
IOH = 50 mA
4.5 V
5.5 V
3.94
3.8 3.7
3.85
IOH = 75 mA
5.5 V
3.85
V
IOL = 50 µA
4.5 V
0.1 0.1 0.1
VOL
VI = VIH or VIL
IOL = 24 mA
IOL = 50 mA
IOL = 75 mA
4.5 V
5.5 V
5.5 V
0.36 0.44
0.5
V
1.65
1.65
II VI = VCC or GND
5.5 V
±0.1 ±1 ±1 µA
ICC VI = VCC or GND, IO = 0
5.5 V
4 40 80 µA
ICC
VI = VCC 2.1 V
4.5 V to 5.5 V 2.4 2.8
3 mA
Ci 10 10 10 pF
Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize
power dissipation. Test verifies a minimum 50-transmission-line drive capability at 85°C and 75-transmission-line drive capability at 125°C.
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Features CD54ACT00, CD74ACT00 QUADRUPLE 2-INPUT P OSITIVE-NAND GATES D Inputs Are TTL-Vo ltage Compatible D Speed of Bipolar F, AS, and S, With Significantly Reduced P ower Consumption D Balanced Propagation Delays D ±24-mA Output Drive Current – Fanout to 15 F Devices D SCR-Latchu p-Resistant CMOS Process and Circuit De sign D Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015 SCHS308B – JANUARY 2001 – REVISED JUNE 2002 CD54 ACT00 . . . F PACKAGE CD74ACT00 . . . E OR M PACKAGE (TOP VIEW) 1A 1B 1Y 2A 2 B 2Y GND 1 2 3 4 5 6 7 14 VCC 13 4B 1 2 4A 11 4Y 10 3B 9 3A 8 3Y description The ‘ACT00 devices contain four ind ependent 2-input NAND gates. Each gate performs the Boolean function of Y = A S B or Y = A + B in positive logic. OR DERING INFORMATION TA PACKAGE† ORD ERABLE PART NUMBER TOP-SIDE MARKING P DIP – E Tube CD74ACT00E CD74ACT00E Tube –55°C to 125°C SOIC – M Tap e and reel CD74ACT00M CD74ACT00M96 AC T00M CDIP – F Tube CD54ACT00F3A CD54ACT00F3A † Package drawings, standard packi.
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