CD54AC08 GATES Datasheet

CD54AC08 Datasheet, PDF, Equivalent


Part Number

CD54AC08

Description

QUADRUPLE 2-INPUT POSITIVE-AND GATES

Manufacture

etcTI

Total Page 16 Pages
Datasheet
Download CD54AC08 Datasheet


CD54AC08
CD54AC08, CD74AC08
QUADRUPLE 2-INPUT POSITIVE-AND GATES
D AC Types Feature 1.5-V to 5.5-V Operation
and Balanced Noise Immunity at 30% of the
Supply Voltage
D Speed of Bipolar F, AS, and S, With
Significantly Reduced Power Consumption
D Balanced Propagation Delays
D Buffered Inputs
D ±24-mA Output Drive Current
– Fanout to 15 F Devices
D SCR-Latchup-Resistant CMOS Process and
Circuit Design
D Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
SCHS307C – JANUARY 2001 – REVISED JUNE 2002
CD54AC08 . . . F PACKAGE
CD74AC08 . . . E OR M PACKAGE
(TOP VIEW)
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
14 VCC
13 4B
12 4A
11 4Y
10 3B
9 3A
8 3Y
description
The ’AC08 devices are quadruple 2-input positive-AND gates. These devices perform the Boolean function
+ + )Y A B or Y A B in positive logic.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – E Tube
CD74AC08E
CD74AC08E
Tube
–55°C to 125°C SOIC – M
Tape and reel
CD74AC08M
CD74AC08M96
AC08M
CDIP – F Tube
CD54AC08F3A CD54AC08F3A
Package drawings, standard packing quantities, thermal data, symbolization, and PCB
design guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
(each gate)
INPUTS
AB
OUTPUT
Y
HH
H
LX
L
XL
L
logic diagram, each gate (positive logic)
A
Y
B
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1

CD54AC08
CD54AC08, CD74AC08
QUADRUPLE 2-INPUT POSITIVE-AND GATES
SCHS307C JANUARY 2001 REVISED JUNE 2002
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 6 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): E package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
M package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditionsis not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
TA = 25°C
MIN MAX
40°C TO
85°C
MIN MAX
55°C TO
125°C
MIN MAX
UNIT
VCC Supply voltage
1.5 5.5 1.5 5.5 1.5 5.5 V
VCC = 1.5 V
1.2 1.2 1.2
VIH High-level input voltage
VCC = 3 V
2.1 2.1 2.1 V
VCC = 5.5 V
3.85 3.85 3.85
VCC = 1.5 V
0.3 0.3 0.3
VIL Low-level input voltage
VCC = 3 V
0.9 0.9 0.9 V
VCC = 5.5 V
1.65 1.65 1.65
VI Input voltage
0 VCC
0 VCC
0 VCC V
VO Output voltage
0 VCC
0 VCC
0 VCC V
IOH High-level output current
VCC = 4.5 V to 5.5 V
24 24 24 mA
IOL Low-level output current
VCC = 4.5 V to 5.5 V
24 24 24 mA
t/v Input transition rise or fall rate
VCC = 1.5 V to 3 V
VCC = 3.6 V to 5.5 V
50 50 50
ns/V
20 20 20
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Features CD54AC08, CD74AC08 QUADRUPLE 2-INPUT POS ITIVE-AND GATES D AC Types Feature 1.5 -V to 5.5-V Operation and Balanced Nois e Immunity at 30% of the Supply Voltage D Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption D Balanced Propagation Delays D Buffer ed Inputs D ±24-mA Output Drive Curren t – Fanout to 15 F Devices D SCR-Latc hup-Resistant CMOS Process and Circuit Design D Exceeds 2-kV ESD Protection Pe r MIL-STD-883, Method 3015 SCHS307C JANUARY 2001 – REVISED JUNE 2002 CD 54AC08 . . . F PACKAGE CD74AC08 . . . E OR M PACKAGE (TOP VIEW) 1A 1B 1Y 2A 2 B 2Y GND 1 2 3 4 5 6 7 14 VCC 13 4B 1 2 4A 11 4Y 10 3B 9 3A 8 3Y description The ’AC08 devices are quadruple 2-in put positive-AND gates. These devices p erform the Boolean function + + )Y A B or Y A B in positive logic. ORDERI NG INFORMATION TA PACKAGE† ORDERAB LE PART NUMBER TOP-SIDE MARKING PDIP – E Tube CD74AC08E CD74AC08E Tube –55°C to 125°C SOIC – M Tape and reel CD74AC08M CD74AC08M96 AC08M CDIP – F .
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