SN54AHC240 BUFFERS/DRIVERS Datasheet

SN54AHC240 Datasheet, PDF, Equivalent


Part Number

SN54AHC240

Description

OCTAL BUFFERS/DRIVERS

Manufacture

etcTI

Total Page 22 Pages
Datasheet
Download SN54AHC240 Datasheet


SN54AHC240
D Operating Range 2-V to 5.5-V VCC
D Latch-Up Performance Exceeds 250 mA
Per JESD 17
description/ordering information
These octal buffers/drivers are designed
specifically to improve the performance and
density of 3-state memory-address drivers, clock
drivers, and bus-oriented receivers and
transmitters.
The ’AHC240 devices are organized as two 4-bit
buffers/line drivers with separate output-enable
(OE) inputs. When OE is low, the device passes
data from the A inputs to the Y outputs. When OE
is high, the outputs are in the high-impedance
state.
To ensure the high-impedance state during power
up or power down, OE should be tied to VCC
through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking
capability of the driver.
SN54AHC240, SN74AHC240
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS251H – OCTOBER 1995 – REVISED JULY 2003
SN54AHC240 . . . J OR W PACKAGE
SN74AHC240 . . . DB, DGV, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
1
2
3
4
5
6
7
8
9
10
20 VCC
19 2OE
18 1Y1
17 2A4
16 1Y2
15 2A3
14 1Y3
13 2A2
12 1Y4
11 2A1
SN54AHC240 . . . FK PACKAGE
(TOP VIEW)
3 2 1 20 19
1A2 4
18 1Y1
2Y3 5
17 2A4
1A3 6
16 1Y2
2Y2 7
15 2A3
1A4
8 14
9 10 11 12 13
1Y3
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – N
Tube
SN74AHC240N
SN74AHC240N
SOIC – DW
Tube
Tape and reel
SN74AHC240DW
SN74AHC240DWR
AHC240
–40°C to 85°C
SOP – NS
SSOP – DB
Tape and reel
Tape and reel
SN74AHC240NSR
SN74AHC240DBR
AHC240
HA240
TSSOP – PW
Tube
Tape and reel
SN74AHC240PW
SN74AHC240PWR
HA240
TVSOP – DGV
Tape and reel SN74AHC240DGVR
HA240
CDIP – J
Tube
SNJ54AHC240J
SNJ54AHC240J
–55°C to 125°C CFP – W
Tube
SNJ54AHC240W
SNJ54AHC240W
LCCC – FK
Tube
SNJ54AHC240FK
SNJ54AHC240FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1

SN54AHC240
SN54AHC240, SN74AHC240
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCLS251H OCTOBER 1995 REVISED JULY 2003
logic diagram (positive logic)
1
1OE
2
1A1
FUNCTION TABLE
(each 4-bit buffer/driver)
INPUTS
OE A
OUTPUT
Y
LH
L
LL
H
HX
Z
18
1Y1
19
2OE
11
2A1
9
2Y1
1A2 4
16 1Y2
2A2 13
7 2Y2
1A3 6
14 1Y3
2A3 15
5 2Y3
1A4 8
12 1Y4
2A4 17
3 2Y4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 7 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±75 mA
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65°C to 150°C
Stresses beyond those listed under absolute maximum ratingsmay cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditionsis not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Features D Operating Range 2-V to 5.5-V VCC D Lat ch-Up Performance Exceeds 250 mA Per JE SD 17 description/ordering information These octal buffers/drivers are designe d specifically to improve the performan ce and density of 3-state memory-addres s drivers, clock drivers, and bus-orien ted receivers and transmitters. The ’ AHC240 devices are organized as two 4-b it buffers/line drivers with separate o utput-enable (OE) inputs. When OE is lo w, the device passes data from the A in puts to the Y outputs. When OE is high, the outputs are in the high-impedance state. To ensure the high-impedance sta te during power up or power down, OE sh ould be tied to VCC through a pullup re sistor; the minimum value of the resist or is determined by the current-sinking capability of the driver. SN54AHC240, SN74AHC240 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCLS251H – OCTOBER 19 95 – REVISED JULY 2003 SN54AHC240 . . . J OR W PACKAGE SN74AHC240 . . . DB, DGV, DW, N, NS, OR PW PACKAGE (TOP VIEW) 1OE 1A1 2Y4 1A2 2Y3 1A3 2Y2.
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