SN74S373 FLIP-FLOPS Datasheet

SN74S373 Datasheet, PDF, Equivalent


Part Number

SN74S373

Description

OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS

Manufacture

etcTI

Total Page 30 Pages
Datasheet
Download SN74S373 Datasheet


SN74S373
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B – OCTOBER 1975 – REVISED AUGUST 2002
D Choice of Eight Latches or Eight D-Type
Flip-Flops in a Single Package
D 3-State Bus-Driving Outputs
D Full Parallel Access for Loading
D Buffered Control Inputs
D Clock-Enable Input Has Hysteresis to
Improve Noise Rejection (’S373 and ’S374)
D P-N-P Inputs Reduce DC Loading on Data
Lines (’S373 and ’S374)
description
These 8-bit registers feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. The
high-impedance 3-state and increased
high-logic-level drive provide these registers with
the capability of being connected directly to and
driving the bus lines in a bus-organized system
without need for interface or pullup components.
These devices are particularly attractive for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
The eight latches of the ’LS373 and ’S373 are
transparent D-type latches, meaning that while
the enable (C or CLK) input is high, the Q outputs
follow the data (D) inputs. When C or CLK is taken
low, the output is latched at the level of the data
that was set up.
SN54LS373, SN54LS374, SN54S373,
SN54S374 . . . J OR W PACKAGE
SN74LS373, SN74S374 . . . DW, N, OR NS PACKAGE
SN74LS374 . . . DB, DW, N, OR NS PACKAGE
SN74S373 . . . DW OR N PACKAGE
(TOP VIEW)
OC
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
1
2
3
4
5
6
7
8
9
10
20 VCC
19 8Q
18 8D
17 7D
16 7Q
15 6Q
14 6D
13 5D
12 5Q
11 C
C for ’LS373 and ’S373; CLK for ’LS374 and ’S374.
SN54LS373, SN54LS374, SN54S373,
SN54S374 . . . FK PACKAGE
(TOP VIEW)
2D
3 2 1 20 19
4 18
8D
2Q 5
17 7D
3Q 6
16 7Q
3D 7
15 6Q
4D 8
14 6D
9 10 11 12 13
The eight flip-flops of the ’LS374 and ’S374 are
edge-triggered D-type flip-flops. On the positive
transition of the clock, the Q outputs are set to the
logic states that were set up at the D inputs.
C for ’LS373 and ’S373; CLK for ’LS374 and ’S374.
Schmitt-trigger buffered inputs at the enable/clock lines of the ’S373 and ’S374 devices simplify system design
as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered
output-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logic
levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly.
OC does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new
data can be entered, even while the outputs are off.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2002, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1

SN74S373
SN54LS373, SN54LS374, SN54S373, SN54S374,
SN74LS373, SN74LS374, SN74S373, SN74S374
OCTAL D-TYPE TRANSPARENT LATCHES AND EDGE-TRIGGERED FLIP-FLOPS
SDLS165B OCTOBER 1975 REVISED AUGUST 2002
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
Tube
SN74LS373N
SN74LS373N
PDIP N
Tube
Tube
SN74LS374N
SN74S373N
SN74LS374N
SN74S373N
Tube
SN74S374N
SN74S374N
Tube
Tape and reel
SN74LS373DW
SN74LS373DWR
LS373
0°C to 70°C
SOIC DW
Tube
Tape and reel
Tube
Tape and reel
SN74LS374DW
SN74LS374DWR
SN74S373DW
SN74S373DWR
LS374
S373
Tube
Tape and reel
SN74S374DW
SN74S374DWR
S374
Tape and reel SN74LS373NSR 74LS373
SOP NS Tape and reel SN74LS374NSR 74LS374
Tape and reel SN74S374NSR
74S374
SSOP DB Tape and reel SN74LS374DBR LS374A
Tube
SN54LS373J
SN54LS373J
Tube
SNJ54LS373J
SNJ54LS373J
Tube
SN54LS374J
SN54LS374J
CDIP J
Tube
Tube
SNJ54LS374J
SN54S373J
SNJ54LS374J
SN54S373J
Tube
SNJ54S373J
SNJ54S373J
Tube
SN54S374J
SN54S374J
55°C to 125°C
Tube
SNJ54S374J
SNJ54S374J
Tube
SNJ54LS373W
SNJ54LS373W
CFP W
Tube
SNJ54LS374W
SNJ54LS374W
Tube
SNJ54S374W
SNJ54S374W
Tube
SNJ54LS373FK SNJ54LS373FK
Tube
LCCC FK
Tube
SNJ54LS374FK
SNJ54S373FK
SNJ54LS374FK
SNJ54S373FK
Tube
SNJ54S374FK
SNJ54S374FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Features SN54LS373, SN54LS374, SN54S373, SN54S374 , SN74LS373, SN74LS374, SN74S373, SN74S 374 OCTAL D-TYPE TRANSPARENT LATCHES AN D EDGE-TRIGGERED FLIP-FLOPS SDLS165B OCTOBER 1975 – REVISED AUGUST 2002 D Choice of Eight Latches or Eight D-T ype Flip-Flops in a Single Package D 3- State Bus-Driving Outputs D Full Parall el Access for Loading D Buffered Contro l Inputs D Clock-Enable Input Has Hyste resis to Improve Noise Rejection (’S3 73 and ’S374) D P-N-P Inputs Reduce D C Loading on Data Lines (’S373 and S374) description These 8-bit register s feature 3-state outputs designed spec ifically for driving highly capacitive or relatively low-impedance loads. The high-impedance 3-state and increased hi gh-logic-level drive provide these regi sters with the capability of being conn ected directly to and driving the bus l ines in a bus-organized system without need for interface or pullup components . These devices are particularly attrac tive for implementing buffer registers, I/O ports, bidirectional bus driver.
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