X55060 Monitor Datasheet

X55060 Datasheet, PDF, Equivalent


Part Number

X55060

Description

64K Dual Voltage Monitor

Manufacture

Renesas

Total Page 23 Pages
Datasheet
Download X55060 Datasheet


X55060
DATASHEET
X55060
64K Dual Voltage Monitor with Integrated System Battery Switch and EEPROM
FN8133
Rev 0.00
March 28, 2005
FEATURES
• Dual voltage monitoring
• Active high and active low reset outputs
• Four standard reset threshold voltages
(4.6/2.9, 4.6/2.6, 2.9/1.6, 2.6/1.6)
—User programmable thresholds
• Lowline Output — Zero delayed POR
• Reset signal valid to VCC = 1V
• System battery switch-over circuitry
• Long battery life with low power consumption
—<50µA max standby current, watchdog on
—<30µA max standby current, watchdog off
• Selectable watchdog timer
—(0.15s, 0.4s, 0.8s, off)
• 64Kbits of EEPROM
• Built-in inadvertent write protection
—Power-up/power-down protection circuitry
—Protect none(0), or all of EEPROM array with
programmable Block Lockprotection
—In circuit programmable ROM mode
BLOCK DIAGRAM
• Minimize EEPROM programming time
—64 byte page write mode
—Self-timed write cycle
—5ms write cycle time (typical)
• 10MHz SPI interface modes (0,0 & 1,1)
• 2.7V to 5.5V power supply operation
• Available packages — 20-lead TSSOP
DESCRIPTION
This device combines power-on reset control, battery
switch circuit, watchdog timer, supply voltage supervi-
sion, secondary voltage supervision, block lock protect
and serial EEPROM in one package. This combination
lowers system cost, reduces board space require-
ments, and increases reliability.
Applying power to the device activates the power-on
reset circuit which holds RESET/RESET active for a
period of time. This allows the power supply and oscilla-
tor to stabilize before the processor can execute code.
V2MON
WP
SO
SI
SCK
CS
Watchdog Transition
Detector
Data
Register
Command
Decode, Test
& Control
Logic
V2 Monitor
Logic
+
V-TRIP2
VOUT
Protect Logic
Status
Register
EEPROM Array
512 X 128
Watchdog
Timer Reset
Reset &
Watchdog
Timebase
V2FAIL
WDO
RESET
BATT-ON
VOUT
VBATT
VCC
(V1MON)
System
Battery
Switch
VCCLoMgiocnitor
+
V-TRIP1
VOUT
Power-on,
Low Voltage
Reset
Generation
RESET/MR
LOWLINE
FN8133 Rev 0.00
March 28, 2005
Page 1 of 23

X55060
X55060
X55060
A system battery switch circuit compares VCC (V1MON)
with VBATT input and connects VOUT to whichever is
higher. This provides voltage to external SRAM or other
circuits in the event of main power failure. The X55060
can drive 50mA from VCC and 250µA from VBATT. The
device switches to VBATT when VCC drops below the low
VCC voltage threshold and VBATT > VCC.
The Watchdog Timer provides an independent protec-
tion mechanism for microcontrollers. When the micro-
controller fails to restart a timer within a selectable time
out interval, the device activates the WDO signal. The
user selects the interval from three preset values. Once
selected, the interval does not change, even after
cycling the power.
The device’s low VCC detection circuitry protects the
user’s system from low voltage conditions, resetting the
system when VCC (V1MON) falls below the minimum VCC
trip point (VTRIP1). RESET/RESET is asserted until VCC
returns to proper operating level and stabilizes. A second
voltage monitor circuit tracks the unregulated supply or
monitors a second power supply voltage to provide a
power fail warning. Intersil’s unique circuits allow the
threshold for either voltage monitor to be reprogrammed
to meet special needs or to fine-tune the threshold for
applications requiring higher precision.
ORDERING INFORMATION
X55060
Suffix
V20-4.5A
V20I-4.5A
V20-4.5
V20I-4.5
V20-2.7A
V20I-2.7A
V20-2.7
V20I-2.7
Vtrip1
4.6
4.6
2.9
2.6
Vtrip2
2.6
2.9
1.65
1.65
Temp Range
0°C to 70°C
-40°C to 85°C
0°C to 70°C
-40°C to 85°C
0°C to 70°C
-40°C to 85°C
0°C to 70°C
-40°C to 85°C
PIN CONFIGURATION
20-Pin TSSOP
CS/WDI
NC
SO
RESET
LOWLINE
V2FAIL
V2MON
WP
NC
VSS
1
2
3
4
5
6
7
8
9
10
20 VCC (V1MON)
19 WDO
18 RESET/MR
17 BATT-ON
16 VOUT
15 VBATT
14 SCK
13 NC
12 NC
11 SI
FN8133 Rev 0.00
March 28, 2005
Page 2 of 23


Features DATASHEET X55060 64K Dual Voltage Monit or with Integrated System Battery Switc h and EEPROM FN8133 Rev 0.00 March 28, 2005 FEATURES • Dual voltage monito ring • Active high and active low res et outputs • Four standard reset thre shold voltages (4.6/2.9, 4.6/2.6, 2.9/1 .6, 2.6/1.6) —User programmable thres holds • Lowline Output — Zero delay ed POR • Reset signal valid to VCC = 1V • System battery switch-over circu itry • Long battery life with low pow er consumption —<50µA max standby cu rrent, watchdog on —<30µA max standb y current, watchdog off • Selectable watchdog timer —(0.15s, 0.4s, 0.8s, o ff) • 64Kbits of EEPROM • Built-in inadvertent write protection —Power-u p/power-down protection circuitry —Pr otect none(0), or all of EEPROM array w ith programmable Block Lock™ protecti on —In circuit programmable ROM mode BLOCK DIAGRAM • Minimize EEPROM prog ramming time —64 byte page write mode —Self-timed write cycle —5ms write cycle time (typical) • 10MHz SPI interface modes (0,0 & 1,1) • 2.7V to .
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