ICS501 MULTIPLIER Datasheet

ICS501 Datasheet, PDF, Equivalent


Part Number

ICS501

Description

PLL CLOCK MULTIPLIER

Manufacture

Renesas

Total Page 10 Pages
Datasheet
Download ICS501 Datasheet


ICS501
LOCO™ PLL CLOCK MULTIPLIER
DATASHEET
ICS501
Description
The ICS501 LOCOTM is the most cost effective way to
generate a high-quality, high-frequency clock output from a
lower frequency crystal or clock input. The name LOCO
stands for Low Cost Oscillator, as it is designed to replace
crystal oscillators in most electronic systems. Using
Phase-Locked Loop (PLL) techniques, the device uses a
standard fundamental mode, inexpensive crystal to
produce output clocks up to 160 MHz.
Stored in the chip’s ROM is the ability to generate nine
different multiplication factors, allowing one chip to output
many common frequencies (see table on page 2).
The device also has an output enable pin which tri-states
the clock output when the OE pin is taken low.
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input to
output skew and jitter are not defined or guaranteed. For
applications which require defined input to output skew, use
the ICS570B.
Block Diagram
Features
Packaged as 8-pin SOIC, MSOP, or die
RoHS 5 (green) or RoHS 6 (green and lead free)
compliant packaging
IDT’s lowest cost PLL clock
Zero ppm multiplication error
Input crystal frequency of 5 - 27 MHz
Input clock frequency of 2 - 50 MHz
Output clock frequencies up to 160 MHz
Extremely low jitter of 25 ps (one sigma)
Compatible with all popular CPUs
Duty cycle of 45/55 up to 160 MHz
Nine selectable frequencies
Operating voltage of 3.3 V or 5.0 V
Tri-state output for board level testing
25 mA drive capability at TTL levels
Ideal for oscillator replacement
Industrial temperature version available
Advanced, low-power CMOS process
VDD
S1:0 2
Crystal or
Clock input
X1/ICLK
X2
Crystal
O s c illa to r
Optional crystal capacitors
PLL Clock
M u ltip lie r
Circuitry
and ROM
GND
OE
CLK
IDT™ / ICS™ LOCO™ PLL CLOCK MULTIPLIER
1
ICS501
REV S 20170331

ICS501
ICS501
LOCO™ PLL CLOCK MULTIPLIER
CLOCK MULTIPLIER
Pin Assignment
X1/ I CLK
VDD
GND
S1
1
2
3
4
8 X2
7 OE
6 S0
5 CLK
8 Pi n ( 150 mi l ) SOI C
Clock Output Table
S1 S0
00
0M
01
M0
MM
M1
10
1M
11
CLK
4X input
5.3125X input
5X input
6.25X input
2X input
3.125X input
6X input
3X input
8X input
Minimum Input
per page 5
20 MHz
per page 5
4 MHz
per page 5
8 MHz
per page 5
per page 5
per page 5
0 = connect directly to ground
1 = connect directly to VDD
M = leave unconnected (floating)
Common Output Frequency Examples (MHz)
Output
20 24 30 32 33.33 37.5 40 48
50 60 62.5
Input
10 12 10 16 16.66 12 10 12 16.66 10 20
Selection (S1, S0) M, M M, M 1, M M, M M, M M, 1 0, 0 0, 0 1, M 1, 0 M, 1
Output
64 66.66 72 75 80 83.33 90 100 106.25 120 125
Input
16 16.66 12 12 10 16.66 15 20
20 15 20
Selection (S1, S0) 0, 0 0, 0 1, 0 M, 0 1, 1 0, 1 1, 0 0, 1 0, M 1, 1 M, 0
Pin Descriptions
Pin Pin
Number Name
1 XI/ICLK
2 VDD
3 GND
4 S1
5 CLK
6 S0
7 OE
8 X2
Pin
Type
Input
Power
Power
Tri-level Iinput
Output
Tri-level Input
Input
Output
Pin Description
Crystal connection or clock input.
Connect to +3.3 V or +5 V.
Connect to ground.
Select 1 for output clock. Connect to GND or VDD or float.
Clock output per table above.
Select 0 for output clock. Connect to GND or VDD or float.
Output enable. Tri-states CLK output when low. Internal pull-up.
Crystal connection. Leave unconnected for clock input.
IDT™ / ICS™ LOCO™ PLL CLOCK MULTIPLIER
2
ICS501
REV S 20170331


Features LOCO™ PLL CLOCK MULTIPLIER DATASHEET ICS501 Description The ICS501 LOCOTM i s the most cost effective way to genera te a high-quality, high-frequency clock output from a lower frequency crystal or clock input. The name LOCO stands fo r Low Cost Oscillator, as it is designe d to replace crystal oscillators in mos t electronic systems. Using Phase-Locke d Loop (PLL) techniques, the device use s a standard fundamental mode, inexpens ive crystal to produce output clocks up to 160 MHz. Stored in the chip’s ROM is the ability to generate nine differ ent multiplication factors, allowing on e chip to output many common frequencie s (see table on page 2). The device als o has an output enable pin which tri-st ates the clock output when the OE pin i s taken low. This product is intended f or clock generation. It has low output jitter (variation in the output period) , but input to output skew and jitter a re not defined or guaranteed. For appli cations which require defined input to output skew, use the ICS570B.
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