Document
IDT54/74FCT573T/AT/CT FASTCMOSOCTALTRANSPARENTLATCH
MILITARYANDINDUSTRIALTEMPERATURERANGES
FAST CMOS OCTAL TRANSPARENT LATCH
IDT54/74FCT573T/AT/CT
FEATURES:
• Std., A, and C grades • Low input and output leakage ≤1µA (max.) • CMOS power levels • True TTL input and output compatibility:
– VOH = 3.3V (typ.) – VOL = 0.3V (typ.) • High Drive outputs (-15mA IOH, 48mA IOL) • Meets or exceeds JEDEC standard 18 specifications • Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) • Power off disable outputs permit "live insertion" • Available in the following packages: – Industrial: SOIC, QSOP – Military: CERDIP, LCC
DESCRIPTION:
The FCT573Tis an octal transparent latch built using an advanced dual metal CMOS technology. These octal latches have 3-state outputs and are intended for bus oriented applications. The flip-flops appear transparent to the data when Latch Enable (LE) is high. When LE is low, the data that meets the set-up time is latched. Data appears on the bus when the Output Enable (OE) is low. When OE is high, the bus output is in the high-impedance state.
FUNCTIONAL BLOCK DIAGRAM
D0 D1 D2 D3 D4 D5 D6 D7
D O
G
D O
G
D O
G
D O
G
D O
G
D O
G
D O
G
D O
G
LE
OE O0 O1 O2 O3 O4 O5 O6 O7
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
MILITARY AND INDUSTRIAL TEMPERATURE RANGES
1
NOVEMBER 2016
DSC-5948/8
IDT54/74FCT573T/AT/CT FASTCMOSOCTALTRANSPARENTLATCH
PIN CONFIGURATION
OE D0 D1 D2 D3 D4 D5 D6 D7 GND
1 2 3 4 5 6 7 8 9 10
20 VCC 19 O0 18 O1 17 O2 16 O3 15 O4 14 O5 13 O6 12 O7 11 LE
D7 GND
LE O7 O6
MILITARYANDINDUSTRIALTEMPERATURERANGES
D1 D0 OE VCC O0
INDEX
32
20 19
D2 4
1 18 O1
D3 5
17 O2
D4 6
16 O3
D5 7
15 O4
D6 8
14 O5
9 10 11 12 13
CERDIP/ SOIC/ QSOP TOP VIEW
LCC TOP VIEW
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM(2) VTERM(3) TSTG IOUT
Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Storage Temperature DC Output Current
Max –0.5 to +7 –0.5 to VCC+0.5 –65 to +150 –60 to +120
Unit V V °C mA
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5V unless otherwise noted. 2. Inputs and Vcc terminals only. 3. Output and I/O terminals only.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
Parameter(1)
Conditions Typ. Max. Unit
CIN Input Capacitance VIN = 0V 6 10 pF
COUT
Output Capacitance VOUT = 0V
8
12 pF
NOTE: 1. This parameter is measured at characterization but not tested.
PIN DESCRIPTION
Pin Names
Description
Dx DataInputs
LE Latch Enable Input (Active HIGH)
OE Output Enable Input (Active LOW)
O x 3-StateOut.