9FGV0441 GENERATOR Datasheet

9FGV0441 Datasheet, PDF, Equivalent


Part Number

9FGV0441

Description

4-OUTPUT VERY LOW POWER PCIE GEN 1-4 CLOCK GENERATOR

Manufacture

Renesas

Total Page 17 Pages
Datasheet
Download 9FGV0441 Datasheet


9FGV0441
4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR
DATASHEET
9FGV0441
Description
The 9FGV0441 is an 4-output very low power clock
generator for PCIe Gen 1, 2, 3 and 4 applications with
integrated output terminations providing Zo = 100. The
device has 4 output enables for clock management and
supports 2 different spread spectrum levels in addition to
spread off.
Recommended Application
PCIe Gen1–4 clock generation for Riser Cards, Storage,
Networking, JBOD, Communications, Access Points
Output Features
4 0.7V low-power HCSL-compatible (LP-HCSL) DIF
pairs with Zo=100
1 1.8V LVCMOS REF output with Wake-On-Lan (WOL)
support
Key Specifications
DIF cycle-to-cycle jitter < 50ps
DIF output-to-output skew < 50ps
DIF phase jitter is PCIe Gen1–4 compliant
REF phase jitter is < 1.5ps RMS
Block Diagram
Features/Benefits
Integrated terminations provide 100differential Zo;
reduced component count and board space
1.8V operation; reduced power consumption
OE# pins; support DIF power management
LP-HCSL differential clock outputs; reduced power and
board space
Programmable slew rate for each output; allows tuning
for various line lengths
Programmable output amplitude; allows tuning for
various application environments
DIF outputs blocked until PLL is locked; clean system
start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
3.3V tolerant SMBus interface works with legacy
controllers
Space saving 5 x 5 mm 32-VFQFPN; minimal board
space
Selectable SMBus addresses; multiple devices can
easily share an SMBus segment
X1_25
X2
OE(3:0)#
OSC
REF1.8
SS Capable PLL
4
DIF(3:0)
SADR
SS_EN_tri
CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
IDT® 4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR
1
9FGV0441
JUNE 6, 2019

9FGV0441
9FGV0441
4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR
Pin Configuration
GNDXTAL 1
XIN/CLKIN_25 2
X2 3
VDDXTAL1.8 4
VDDREF1.8 5
vSADR/REF1.8 6
GNDREF 7
GNDDIG 8
32 31 30 29 28 27 26 25
9FGV0441
9 10 11 12 13 14 15 16
24 vOE2#
23 DIF2#
22 DIF2
21 VDDA1.8
20 GNDA
19 DIF1#
18 DIF1
17 vOE1#
32-VFQFPN, 5 x 5 mm, 0.5mm pitch
^ prefix indicates internal 120kOhm pull-up resistor
v prefix indicates internal 120kOhm pull down-resistor
SMBus Address Selection Table
State of SADR on first application
of CKPWRGD_PD#
SADR
0
1
Address
1101000
1101010
+ Read/Write Bit
x
x
Power Management Table
CKPWRGD_PD#
SMBus
OE bit
DIFx
OEx# True O/P Comp. O/P
REF
0
X X Low
Low Hi-Z1
1
1
0 Running
Running Running
1
0 1 Low
Low Low
1. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when
CKPWRG_PD# is low, REF is Low.
Power Connections
Pin Number
VDD
4
5
9
16, 25
21
GND
1
7
8, 30
15, 26
20
Description
XTAL Analog
REF Output
Digital Power
DIF outputs
PLL Analog
IDT® 4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR
2
9FGV0441
JUNE 6, 2019


Features 4-OUTPUT VERY LOW POWER PCIE GEN 1–4 C LOCK GENERATOR DATASHEET 9FGV0441 Des cription The 9FGV0441 is an 4-output ve ry low power clock generator for PCIe G en 1, 2, 3 and 4 applications with inte grated output terminations providing Zo = 100. The device has 4 output enab les for clock management and supports 2 different spread spectrum levels in ad dition to spread off. Recommended Appli cation PCIe Gen1–4 clock generation f or Riser Cards, Storage, Networking, JB OD, Communications, Access Points Outpu t Features • 4 0.7V low-power HCSL-co mpatible (LP-HCSL) DIF pairs with Zo=10 0 • 1 1.8V LVCMOS REF output with Wake-On-Lan (WOL) support Key Specifica tions • DIF cycle-to-cycle jitter < 5 0ps • DIF output-to-output skew < 50p s • DIF phase jitter is PCIe Gen1–4 compliant • REF phase jitter is < 1. 5ps RMS Block Diagram Features/Benefit s • Integrated terminations provide 1 00 differential Zo; reduced componen t count and board space • 1.8V operation; reduced power consumption • OE# pins; support D.
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