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9FGV0441 Dataheets PDF



Part Number 9FGV0441
Manufacturers Renesas
Logo Renesas
Description 4-OUTPUT VERY LOW POWER PCIE GEN 1-4 CLOCK GENERATOR
Datasheet 9FGV0441 Datasheet9FGV0441 Datasheet (PDF)

4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR DATASHEET 9FGV0441 Description The 9FGV0441 is an 4-output very low power clock generator for PCIe Gen 1, 2, 3 and 4 applications with integrated output terminations providing Zo = 100. The device has 4 output enables for clock management and supports 2 different spread spectrum levels in addition to spread off. Recommended Application PCIe Gen1–4 clock generation for Riser Cards, Storage, Networking, JBOD, Communications, Access Points Out.

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4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR DATASHEET 9FGV0441 Description The 9FGV0441 is an 4-output very low power clock generator for PCIe Gen 1, 2, 3 and 4 applications with integrated output terminations providing Zo = 100. The device has 4 output enables for clock management and supports 2 different spread spectrum levels in addition to spread off. Recommended Application PCIe Gen1–4 clock generation for Riser Cards, Storage, Networking, JBOD, Communications, Access Points Output Features • 4 0.7V low-power HCSL-compatible (LP-HCSL) DIF pairs with Zo=100 • 1 1.8V LVCMOS REF output with Wake-On-Lan (WOL) support Key Specifications • DIF cycle-to-cycle jitter < 50ps • DIF output-to-output skew < 50ps • DIF phase jitter is PCIe Gen1–4 compliant • REF phase jitter is < 1.5ps RMS Block Diagram Features/Benefits • Integrated terminations provide 100 differential Zo; reduced component count and board space • 1.8V operation; reduced power consumption • OE# pins; support DIF power management • LP-HCSL differential clock outputs; reduced power and board space • Programmable slew rate for each output; allows tuning for various line lengths • Programmable output amplitude; allows tuning for various application environments • DIF outputs blocked until PLL is locked; clean system start-up • Selectable 0%, -0.25% or -0.5% spread on DIF outputs; reduces EMI • External 25MHz crystal; supports tight ppm with 0 ppm synthesis error • Configuration can be accomplished with strapping pins; SMBus interface not required for device control • 3.3V tolerant SMBus interface works with legacy controllers • Space saving 5 x 5 mm 32-VFQFPN; minimal board space • Selectable SMBus addresses; multiple devices can easily share an SMBus segment X1_25 X2 OE(3:0)# OSC REF1.8 SS Capable PLL 4 DIF(3:0) SADR SS_EN_tri CKPWRGD_PD# SDATA_3.3 SCLK_3.3 CONTROL LOGIC IDT® 4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR 1 9FGV0441 JUNE 6, 2019 9FGV0441 4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR Pin Configuration vSS_EN_tri ^CKPWRGD_PD# GND vOE3# DIF3# DIF3 GND VDDO1.8 GNDXTAL 1 XIN/CLKIN_25 2 X2 3 VDDXTAL1.8 4 VDDREF1.8 5 vSADR/REF1.8 6 GNDREF 7 GNDDIG 8 32 31 30 29 28 27 26 25 9FGV0441 9 10 11 12 13 14 15 16 24 vOE2# 23 DIF2# 22 DIF2 21 VDDA1.8 20 GNDA 19 DIF1# 18 DIF1 17 vOE1# VDDDIG1.8 SCLK_3.3 SDATA_3.3 vOE0# DIF0 DIF0# GND VDDO1.8 32-VFQFPN, 5 x 5 mm, 0.5mm pitch ^ prefix indicates internal 120kOhm pull-up resistor v prefix indicates internal 120kOhm pull down-resistor SMBus Address Selection Table State of SADR on first application of CKPWRGD_PD# SADR 0 1 Address 1101000 1101010 + Read/Write Bit x x Power Management Table CKPWRGD_PD# SMBus OE bit DIFx OEx# True O/P Comp. O/P REF 0 X X Low Low Hi-Z1 1 1 0 Running Running Running 1 0 1 Low Low Low 1. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when CKPWRG_PD# is low, REF is Low. Power Connections Pin Number VDD 4 5 9 16, 25 21 GND 1 7 8, 30 15, 26 20 Description XTAL Analog REF Output Digital Power DIF outputs PLL Analog IDT® 4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR 2 9FGV0441 JUNE 6, 2019 9FGV0441 4-OUTPUT VERY LOW POWER PCIE GEN 1–4 CLOCK GENERATOR Pin Descriptions Pin# 1 2 3 4 5 Pin Name GNDXTAL XIN/CLKIN_25 X2 VDDXTAL1.8 VDDREF1.8 6 vSADR/REF1.8 7 GNDREF 8 GNDDIG 9 VDDDIG1.8 10 SCLK_3.3 11 SDATA_3.3 12 vOE0# 13 DIF0 14 DIF0# 15 GND 16 VDDO1.8 17 vOE1# 18 DIF1 19 DIF1# 20 GNDA 21 VDDA1.8 22 DIF2 23 DIF2# 24 vOE2# 25 VDDO1.8 26 GND 27 DIF3 28 DIF3# 29 vOE3# 30 GND 31 ^CKPWRGD_PD# 32 vSS_EN_tri Type Pin Description GND GND for XTAL IN Crystal input or Reference Clock input. Nominally 25MHz. OUT Crystal output. PWR Power supply for XTAL, nominal 1.8V PWR VDD for REF output. nominal 1.8V. LATCHED I/O Latch to select SMBus Address/1.8V LVCMOS copy of X1 pin. GND Ground pin for the REF outputs. GND Ground pin for digital circuitry PWR 1.8V digital power (dirty power) IN Clock pin of SMBus circuitry, 3.3V tolerant. I/O Data pin for SMBus circuitry, 3.3V tolerant. IN Active low input for enabling DIF pair 0. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs OUT Differential true clock output OUT Differential Complementary clock output GND Ground pin. PWR Power supply for outputs, nominally 1.8V. IN Active low input for enabling DIF pair 1. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs OUT Differential true clock output OUT Differential Complementary clock output GND Ground pin for the PLL core. PWR 1.8V power for the PLL core. OUT Differential true clock output OUT Differential Complementary clock output IN Active low input for enabling DIF pair 2. This pin has an internal pull-down. 1 =disable outputs, 0 = enable outputs PWR Power supply for outputs, nominally 1.8V. GND Ground pin. OUT Differential true clock output .


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