ICS674-01 DIVIDER Datasheet

ICS674-01 Datasheet, PDF, Equivalent


Part Number

ICS674-01

Description

USER CONFIGURABLE DIVIDER

Manufacture

Renesas

Total Page 9 Pages
Datasheet
Download ICS674-01 Datasheet


ICS674-01
USER CONFIGURABLE DIVIDER
DATASHEET
ICS674-01
Description
The ICS674-01 consists of two separate configurable
dividers. The A Divider is a 7-bit divider and can divide by 3
to 129. The B Divider consists of a 9-bit divider followed by
a post divider. The 9-bit divider can divide by 12 to 519. The
post divider has eight settings of 1, 2, 4, 5, 6, 7, 8, and 10;
giving a maximum total divide of 5190. The A and B
Dividers can be cascaded to give a maximum divide of
669510. The ICS674-01 supports the ICS673 PLL Building
Block and enables the user to build a full custom PLL
synthesizer.
Block Diagram
Features
Packaged in 28-pin SSOP (150 mil body)
Pb (lead) free package, RoHS compliant
General purpose programmable divider
Supports ICS673 PLL Building Block
User determines the divide by setting input pins
Pull-ups on all select inputs
Includes one 7-bit Divider for OUTA
Includes one 9-bit Divider and one selectable Post
Divider for OUTB
Industrial temperature range available
25 mA drive capability at TTL levels
Advanced, low power CMOS process
Operating voltage of 3.3 V or 5 V
A6:A0
7
VDD
2
Divider A
INA (7-Bit)
OUTA
Divider B
INB (9-Bit)
Post
Divider
9
B8:B0
3
GND
3
S2:S0
OUTB
IDT™ / ICS™ USER CONFIGURABLE DIVIDER
1
ICS674-01 REV H 051310

ICS674-01
ICS674-01
USER CONFIGURABLE DIVIDER
CLOCK DIVIDER
Pin Assignment
A5
A6
S0
S1
S2
VDD
INA
INB
GND
B0
B1
B2
B3
B4
1 28
2 27
3 26
4 25
5 24
6 23
7 22
8 21
9 20
10 19
11 18
12 17
13 16
14 15
28 pin (150 mil) SSOP
A4
A3
A2
A1
A0
VDD
OUTA
OUTB
GND
GND
B8
B7
B6
B5
Post Divider Table
S2
Pin 5
0
0
0
0
1
1
1
1
S1
Pin 4
0
0
1
1
0
0
1
1
S0
Pin 3
0
1
0
1
0
1
0
1
Post Divide
10
2
8
4
5
7
1
6
Pin Descriptions
Pin
Number
1, 2, 24 - 28
3-5
6, 23
7
8
9, 19 - 20
10 - 18
21
22
Pin
Name
A5, A6, A0-A4
S0, S1, S2
VDD
INA
INB
GND
B0 - B8
OUTB
OUTA
Pin Type
Pin Description
Input
Input
Power
Input
Input
Power
Input
Output
Output
Divider A word input pins. Forms a number from 1 to 127. Internal pull-up
resistors. See page 3 for details.
Select pins for Post Divider. See table above. Internal pull-up resistors.
Connect to VDD.
Divider A input.
Divider B input.
Connect to ground.
Divider B word input pins. Forms a number from 4 to 511. Internal pull-up
resistors. See page 3 for details.
Divider B output.
Divider A output.
IDT™ / ICS™ USER CONFIGURABLE DIVIDER
2
ICS674-01 REV H 051310


Features USER CONFIGURABLE DIVIDER DATASHEET ICS 674-01 Description The ICS674-01 consi sts of two separate configurable divide rs. The A Divider is a 7-bit divider an d can divide by 3 to 129. The B Divider consists of a 9-bit divider followed b y a post divider. The 9-bit divider can divide by 12 to 519. The post divider has eight settings of 1, 2, 4, 5, 6, 7, 8, and 10; giving a maximum total divi de of 5190. The A and B Dividers can be cascaded to give a maximum divide of 6 69510. The ICS674-01 supports the ICS67 3 PLL Building Block and enables the us er to build a full custom PLL synthesiz er. Block Diagram Features • Package d in 28-pin SSOP (150 mil body) • Pb (lead) free package, RoHS compliant • General purpose programmable divider Supports ICS673 PLL Building Block User determines the divide by settin g input pins • Pull-ups on all select inputs • Includes one 7-bit Divider for OUTA • Includes one 9-bit Divider and one selectable Post Divider for OUTB • Industrial temperature range availa.
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