ICS9LRS3187B HUB Datasheet

ICS9LRS3187B Datasheet, PDF, Equivalent


Part Number

ICS9LRS3187B

Description

PROGRAMMABLE TIMING CONTROL HUB

Manufacture

Renesas

Total Page 21 Pages
Datasheet
Download ICS9LRS3187B Datasheet


ICS9LRS3187B
Datasheet
PROGRAMMABLE TIMING CONTROL HUB FOR
INTEL BASED SYSTEMS
ICS9LRS3187B
Recommended Application:
CK505 version 1.1 clock, with fully integrated voltage regulators
and series resistors
Output Features:
• 2 - CPU differential low power push-pull pairs
• 1 - SRC differential low power push-pull pair
• 1 - SATA differential low power push-pull pair
• 1 - DOT differential low power push-pull pair
• 1 - REF, able to drive 3 loads, 14.318MHz
• 1 - 27MHz_SS/non_SS single-ended output pair
Features/Benefits:
• Supports spread spectrum modulation, 0 to -0.5%
down spread for CPU and SRC clocks
• Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
• Available in commercial (0 to +70°C) and industrial
(-40 to +85°C) temperature ranges
• Meets PCIe Gen2 specifications
Key Specifications:
• CPU outputs cycle-cycle jitter <85ps
• SRC outputs cycle-cycle jitter <125ps
• +/- 100ppm frequency accuracy on all clocks
Pin Configuration
32 31 30 29 28 27 26 25
VDDDOT96MHz_3.3 1
24 VDDCPU_3.3
GNDDOT96MHz 2
23 CPUT0_LPR
DOT96T_LPR 3
22 CPUC0_LPR
9LRS3187DOT96C_LPR 4
VDD_27MHz 5
21 GNDCPU
20 CPUT1_LPR
27MHz_nonSS 6
19 CPUC1_LPR
27MHz_SS 7
18 VDDCPU_IO
GND27MHz 8
17 VDDSRC_3.3
9 10 11 12 13 14 15 16
** Internal Pull-Down Resistor
* Internal Pull-Up Resistor
32-pin MLF
IDT® Programmable Timing Control Hub for Intel Based Systems
1
1602F—11/04/11

ICS9LRS3187B
ICS9LRS3187B
Programmable Timing Control Hub for Intel Based Systems
Pin Description
Pin# Pin Name
Type Pin Description
1 VDDDOT96MHz_3.3
PWR Power pin for the 96MHz output 3.3V.
2 GNDDOT96MHz
PWR Ground pin for the 96MHz output
3 DOT96T_LPR
4 DOT96C_LPR
OUT
OUT
True DOT96 output with integrated 33ohm series resistor. No
50ohm resistor to GND needed.
Complement DOT96 output with integrated 33ohm series
resistor. No 50ohm resistor to GND needed.
5 VDD_27MHz
PWR Power pin for the 27MHz output 3.3V.
6 27MHz_nonSS
OUT 3.3V Single-ended 27MHz non-spread clock.
7 27MHz_SS
OUT 3.3V Single-ended 27MHz spread clock.
8 GND27MHz
OUT Ground pin for the 27MHz outputs.
9 GNDSATA
PWR Ground pin for the SATA outputs.
10 SATAT_LPR
11 SATAC_LPR
OUT
OUT
True clock of differential 0.8V push-pull SATA/SRC output with
integrated 33ohm series resistor. No 50ohm resistor to GND
needed.
Complementary clock of differential 0.8V push-pull SATA/SRC
output with integrated 33ohm series resistor. No 50ohm resistor
to GND needed.
12 GNDSRC
PWR Ground pin for the SRC outputs
13 SRCT1_LPR
14 SRCC1_LPR
OUT
OUT
True clock of differential 0.8V push-pull SRC output with
integrated 33ohm series resistor. No 50ohm resistor to GND
needed.
Complementary clock of differential 0.8V push-pull SRC output
with integrated 33ohm series resistor. No 50ohm resistor to
GND needed.
15 VDDSRC_IO
PWR 1.05V to 3.3V from external power supply
16 *CPU_STOP#
IN Stops all CPU clocks, except those set to be free running
clocks
17 VDDSRC_3.3
PWR Supply for SRC clocks, 3.3V nominal
18 VDDCPU_IO
PWR 1.05V to 3.3V from external power supply
19 CPUC1_LPR
20 CPUT1_LPR
OUT
OUT
Complementary clock of differential pair 0.8V push-pull CPU
outputs with integrated 33ohm series resistor. No 50 ohm
resistor to GND needed.
True clock of differential pair 0.8V push-pull CPU outputs with
integrated 33ohm series resistor. No 50 ohm resistor to GND
needed.
21 GNDCPU
PWR Ground pin for the CPU outputs.
22 CPUC0_LPR
23 CPUT0_LPR
OUT
OUT
Complementary clock of differential pair 0.8V push-pull CPU
outputs with integrated 33ohm series resistor. No 50 ohm
resistor to GND needed.
True clock of differential pair 0.8V push-pull CPU outputs with
integrated 33ohm series resistor. No 50 ohm resistor to GND
needed.
24 VDDCPU_3.3
PWR Supply for CPU clocks, 3.3V nominal
25 CLKPWRGD/PD#_3.3
IN Notifies CK505 to sample latched inputs, or PWRDWN# mode
26 GNDREF
PWR Ground pin for the REF outputs.
27 X2
OUT Crystal output, Nominally 14.318MHz
28 X1
IN Crystal input, Nominally 14.318MHz
29 VDDREF_3.3
PWR Power pin for the XTAL and REF clocks, nominal 3.3V
30 REF_2/FSLC_3.3**
14.318 MHz reference clock, which can drive 2 loads / 3.3V
I/O tolerant input for CPU frequency selection. Refer to input
electrical characteristics for Vil_FS and Vih_FS values.
31 SDATA_3.3
I/O Data pin for SMBus circuitry, 3.3V tolerant
32 SCLK_3.3
IN Clock pin of SMBus circuitry, 3.3V tolerant.
IDT® Programmable Timing Control Hub for Intel Based Systems
2
Datasheet
1602F—11/04/11


Features Datasheet PROGRAMMABLE TIMING CONTROL H UB FOR INTEL BASED SYSTEMS ICS9LRS3187 B Recommended Application: CK505 versi on 1.1 clock, with fully integrated vol tage regulators and series resistors Ou tput Features: • 2 - CPU differential low power push-pull pairs • 1 - SRC differential low power push-pull pair 1 - SATA differential low power push -pull pair • 1 - DOT differential low power push-pull pair • 1 - REF, able to drive 3 loads, 14.318MHz • 1 - 27 MHz_SS/non_SS single-ended output pair Features/Benefits: • Supports spread spectrum modulation, 0 to -0.5% down s pread for CPU and SRC clocks • Uses e xternal 14.318MHz crystal, external cry stal load caps are required for frequen cy tuning • Available in commercial ( 0 to +70°C) and industrial (-40 to +85 °C) temperature ranges • Meets PCIe Gen2 specifications Key Specifications: • CPU outputs cycle-cycle jitter <85 ps • SRC outputs cycle-cycle jitter < 125ps • +/- 100ppm frequency accuracy on all clocks Pin Configuration SCLK_3.3 SDATA_3..
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