9VRS4338D CLOCK Datasheet

9VRS4338D Datasheet, PDF, Equivalent


Part Number

9VRS4338D

Description

VERY LOW POWER CLOCK

Manufacture

Renesas

Total Page 24 Pages
Datasheet
Download 9VRS4338D Datasheet


9VRS4338D
VERY LOW POWER CLOCK FOR 2011 NETBOOKS
DATASHEET
9VRS4338D
General Description
The 9VRS4338D is a main clock for Intel Netbooks,
conforming to the CK-NET specification. It is driven with a
14.31818MHz crystal and generates a variety of clocks,
including an LCD clock. An SMBus interface allows full
control of the device.
Recommended Application
CK-NET
Output Features
2 - 0.8V push-pull differential CPU pairs
3 - 0.8V push-pull differential SRC pairs
1 - 0.8V push-pull differential SATA/SRC pair
1 - 0.8V push-pull differential DOT96/SRC pair
1 - 0.8V push-pull differential LCD100 pair
1 - 0.8V push-pull differential CPU_ITP/SRC pair
3 - PCI (33MHz), 1 free-running
1 - 25MHz _PCI (33MHz)
1 - USB_48MHz
1 - REF, 14.318MHz
Pin Configuration
Features/Benefits
25M output can run in power down; Supports
Wake_On_LAN
Selectable spread % on CPU, SRC, PCI; Supports
margining
External 14.318MHz crystal; Supports tight ppm
CLKREQ# pins; Support SRC power management
Low power differential clock outputs; reduced power and
board space
Integrated 33 ohm series resistors on all differential
outputs; reduced board space
Key Specifications
CPU cycle-to-cycle jitter <85ps
SRC/SATA cycle-to-cycle jitter <85ps
SRC(1:4) are PCIe Gen2 compliant
SRC5 is PCIe Gen1 compliant
±100ppm frequency accuracy on all clocks except 25M
±30ppm frequency accuracy on 25M
48 47 46 45 44 43 42 41 40 39 38 37
X2 1
36 SRC2_LRS
X1 2
35 SRC2#_LRS
VDDREF 3
34 GNDSRC
REF0_2x/FSLC 4
33 SRC3_LRS
SDATA_3.3 5
32 SRC3#_LRS
SCLK_3.3 6
VDDPCI_3.3 7
9VRS4338D
31 PCI_STOP#_3.3
30 VDDSR C_LVIO
vITP_EN/PCI_F1_2x 8
29 SRC4_LRS
FSLB/PCI2_2x 9
28 SRC4#_LRS
CLKREQA#/PCI3_2x 10
27 SATA_LRS
GNDPCI 11
26 SATA#_LRS
GND25 12
25 GNDSATA
13 14 15 16 17 18 19 20 21 22 23 24
48-pin MLF, 6x6 mm, 0.4mm pitch
v prefix indicates internal 120KOhm pull down resistor
^ prefix indicates internal 120KOhm pull up resistor
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS
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9VRS4338D
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9VRS4338D
9VRS4338D
VERY LOW POWER CLOCK FOR 2011 NETBOOKS
Pin Descriptions
PIN #
PIN NAME
1 X2
2 X1
3 VDDREF
4 REF0_2x/FSLC
5 SDATA_3.3
6 SCLK_3.3
7 VDDPCI_3.3
8 vITP_EN/PCI_F1_2x
9 FSLB/PCI2_2x
10 CLKREQA#/PCI3_2x
11 GNDPCI
12 GND25
13 vSEL_PCI/25M_PCI4_2x
14 VDD25
15 VDD48
16 vUSB_48Mhz_2x
17 GND48
18 CLKREQB#
19 DOT96_LRS/SRC5_LRS
20 DOT96#_LRS/SRC5#_LRS
21 VDD_CORE_1.5
22 LCD100_LRS
23 LCD100#_LRS
24 GNDLCD
T YPE
D ESC RIPT ION
OUT Crystal output, Nominally 14.318MHz
IN Crystal input, Nominally 14.318MHz.
PWR Ref, XTAL power s upply, nominal 3.3V
I/O 2x strength 14.318 MHz reference cloc k./ 3.3V tolerant input for CPU frequency
selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values .
I/O Data pin for SMBus circuitry, 3.3V tolerant.
IN Clock pin of SMBus circuitry, 3.3V tolerant.
PWR Power supply for PCI clocks, nominal 3.3V
ITP Enable Latched Input/Free Running PCI clock output.
ITP_Enable Selects the functionality of the CPU_ITP/SRC output as follows:
I/O
1 = CPU_ITP output
0 = SRC output
3.3V tolerant input for CPU frequency s election. Low voltage threshold inputs,
I/O see input electrical characteristics for Vil_FS and Vih_FS values. / 3.3V PCI
clock output.
Active low realtime input pin to enable SRC Outputs / PCI clock output. (pin
I/O function is programmable through SMBus). See CLKREQ# Control Table and
SRC Power Management Table for details.
PWR Ground pin for the PCI outputs
PWR Ground pin for the 25MHz outputs
SEL_PCI 3.3V latched input to select pin functionality for 25M_PCICLK3
output/25M or PCI clock output. This pin has an internal 120Kohm pulldown
I/O resistor. Latch func tionality is as follows:
0 = 25MHz output
1 = 33.3MHz PCICLK
PWR Power pin for the 25MHz output.3.3V
PWR Power pin for the 48MHz output.3.3V
3.3V 48MHz USB clock output. This pin has an internal 120Kohm pull down
OUT
re si stor .
PWR Ground pin for the 48MHz outputs
Output enable for PCI Express (SRC) outputs. SMBus selects which outputs are
co n tr ol le d.
IN 0 = controlled outputs are enabled
1 = controlled outputs are Low/Low
True clock of push-pull DOT96 or SRC clock with integrated series resistor. No
OUT 50 ohm pull down needed. Default is DOT96. After powerup, this pin func tion
may be changed to SRC via SMBus.
Complementary clock of push-pull DOT96 or SRC clock with integrated series
OUT resistor. No 50 ohm pull down needed. Default is DOT96. After powerup, this pin
function may be changed to SRC via SMBus.
PWR Power for PLL c ore components requiring 1.5V
True clock of differential push-pull LCD100 output with integrated 33ohm series
OUT
resistor. No 50ohm resistor to GND needed.
OUT Complementary clock of differential push-pull LCD100 output with integrated
33ohm series resistor. No 50ohm resistor to GND needed.
PWR Ground pin for LCD clock output
IDT® VERY LOW POWER CLOCK FOR 2011 NETBOOKS
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9VRS4338D
REV A 022616


Features VERY LOW POWER CLOCK FOR 2011 NETBOOKS DATASHEET 9VRS4338D General Descriptio n The 9VRS4338D is a main clock for Int el Netbooks, conforming to the CK-NET s pecification. It is driven with a 14.31 818MHz crystal and generates a variety of clocks, including an LCD clock. An S MBus interface allows full control of t he device. Recommended Application CK-N ET Output Features • 2 - 0.8V push-pu ll differential CPU pairs • 3 - 0.8V push-pull differential SRC pairs • 1 - 0.8V push-pull differential SATA/SRC pair • 1 - 0.8V push-pull differentia l DOT96/SRC pair • 1 - 0.8V push-pull differential LCD100 pair • 1 - 0.8V push-pull differential CPU_ITP/SRC pair • 3 - PCI (33MHz), 1 free-running 1 - 25MHz _PCI (33MHz) • 1 - USB_48 MHz • 1 - REF, 14.318MHz Pin Configur ation Features/Benefits • 25M output can run in power down; Supports Wake_O n_LAN • Selectable spread % on CPU, S RC, PCI; Supports margining • Externa l 14.318MHz crystal; Supports tight ppm • CLKREQ# pins; Support SRC power management • Lo.
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