IDT72215LB SyncFIFO Datasheet

IDT72215LB Datasheet, PDF, Equivalent


Part Number

IDT72215LB

Description

CMOS SyncFIFO

Manufacture

Renesas

Total Page 17 Pages
Datasheet
Download IDT72215LB Datasheet


IDT72215LB
CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18,
2,048 x 18, and 4,096 x 18
IDT72205LB, IDT72215LB,
IDT72225LB, IDT72235LB,
IDT72245LB
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
FEATURES:
256 x 18-bit organization array (IDT72205LB)
512 x 18-bit organization array (IDT72215LB)
1,024 x 18-bit organization array (IDT72225LB)
2,048 x 18-bit organization array (IDT72235LB)
4,096 x 18-bit organization array (IDT72245LB)
10 ns read/write cycle time
Empy and Full flags signal FIFO status
Easy expandable in depth and width
Asynchronous or coincident read and write clocks
Programmable Almost-Empty and Almost-Full flags with
default settings
Half-Full flag capability
Dual-Port zero fall-through time architecture
Output enable puts output data bus in high-impedence state
High-performance submicron CMOS technology
Available in a 64-lead thin quad flatpack (TQFP/STQFP)
and plastic leaded chip carrier (PLCC)
Industrial temperature range (–40°C to +85°C) is available
Green parts available, see ordering information
DESCRIPTION:
The IDT72205LB/72215LB/72225LB/72235LB/72245LB are very high
speed, low-power First-In, First-Out (FIFO) memories with clocked read and
write controls. These FIFOs are applicable for a wide variety of data buffering
needs, such as optical disk controllers, Local Area Networks (LANs), and
interprocessor communication.
These FIFOs have 18-bit input and output ports. The input port is controlled
by a free-running clock (WCLK), and an input enable pin (WEN). Data is read
into the synchronous FIFO on every clock when WEN is asserted. The output
port is controlled by another clock pin (RCLK) and another enable pin (REN).
The read clock can be tied to the write clock for single clock operation or the
two clocks can run asynchronous of one another for dual-clock operation. An
Output Enable pin (OE) is provided on the read port for three-state control of
the output.
The synchronous FIFOs have two fixed flags, Empty (EF) and Full (FF),
and two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF). The
offset loading of the programmable flags is controlled by a simple state machine,
andisinitiatedbyassertingtheLoadpin(LD). A Half-Full flag (HF)isavailable
when the FIFO is used in a single device configuration.
These devices are depth expandable using a Daisy-Chain technique. The
XI and XO pins are used to expand the FIFOs. In depth expansion configu-
ration, First Load (FL) is grounded on the first device and set to HIGH for all
other devices in the Daisy Chain.
The IDT72205LB/72215LB/72225LB/72235LB/72245LB is fabricated
using high-speed submicron CMOS technology.
FUNCTIONAL BLOCK DIAGRAM
WCLK
D0-D17
( )/
WRITE CONTROL
LOGIC
WRITE POINTER
EXPANSION LOGIC
RESET LOGIC
INPUT REGISTER
••
RAM ARRAY
256 x 18, 512 x 18
1,024 x 18, 2,048 x 18
4,096 x 18
••
OUTPUT REGISTER
OFFSET REGISTER
FLAG
LOGIC
READ POINTER
READ CONTROL
LOGIC
/( )
Q0-Q17
RCLK
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
©2017 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
2766 drw 01
NOVEMBER 2017
DSC-2766/4

IDT72215LB
IDT72205LB/72215LB/72225LB/72235LB/72245LB CMOS SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
PIN CONFIGURATIONS
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
D14
D13
D12
D11
D10
D9
VCC
D8
GND
D7
D6
D5
D4
D3
D2
D1
D0
109 8 7
11
6
5
43
2
1
68 67 66 65 64 63 62 6610
59
12 58
13 57
14 56
15 55
16 54
17 53
18 52
19 51
20 50
21 49
22 48
23 47
24 46
25 45
26 44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
VCC
Q14
Q13
GND
Q12
Q11
VCC
Q10
Q9
GND
Q8
Q7
VCC
Q6
Q5
GND
Q4
PLCC (J68-1, order code: J)
TOP VIEW
2766 drw 02
PIN 1
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48 Q14
47 Q13
46 GND
45 Q12
44 Q11
43 VCC
42 Q10
41 Q9
40 GND
39 Q8
38 Q7
37 Q6
36 Q5
35 GND
34 Q4
33 VCC
TQFP (PN64-1, order code: PF)
STQFP (PP64-1, order code: TF)
TOP VIEW
2
2766 drw 03
MARCH 2013


Features CMOS SyncFIFOTM 256 x 18, 512 x 18, 1,02 4 x 18, 2,048 x 18, and 4,096 x 18 IDT 72205LB, IDT72215LB, IDT72225LB, IDT722 35LB, IDT72245LB LEAD FINISH (SnPb) AR E IN EOL PROCESS - LAST TIME BUY EXPIRE S JUNE 15, 2018 FEATURES: • 256 x 18 -bit organization array (IDT72205LB) 512 x 18-bit organization array (IDT7 2215LB) • 1,024 x 18-bit organization array (IDT72225LB) • 2,048 x 18-bit organization array (IDT72235LB) • 4,0 96 x 18-bit organization array (IDT7224 5LB) • 10 ns read/write cycle time Empy and Full flags signal FIFO statu s • Easy expandable in depth and widt h • Asynchronous or coincident read a nd write clocks • Programmable Almost -Empty and Almost-Full flags with defau lt settings • Half-Full flag capabili ty • Dual-Port zero fall-through time architecture • Output enable puts ou tput data bus in high-impedence state High-performance submicron CMOS tech nology • Available in a 64-lead thin quad flatpack (TQFP/STQFP) and plastic leaded chip carrier (PLCC) • Industrial temperature ra.
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