Document
Low Skew, 1-to-15, LVCMOS/LVTTL Clock Generator
87974I
Data Sheet
GENERAL DESCRIPTION
The 87974I is a low skew, low jitter 1-to-15 LVCMOS/ LVTTL Clock Generator/Zero Delay Buffer. The device has a fully integrated PLL and three banks whose divider ratios can be independently controlled, providing output frequency relationships of 1:1, 2:1, 3:1, 3:2, 3:2:1. In addition, the external feedback connection provides for a wide selection of output-to-input frequency ratios. The CLK0 and CLK1 pins allow for redundant clocking on the input and dynamically switching the PLL between two clock sources.
Guaranteed low jitter and output skew characteristics make the 87974I ideal for those applications demanding well defined performance and repeatability.
FEATURES
• Fully integrated PLL • Fifteen single ended 3.3V LVCMOS/LVTTL outputs • Two LVCMOS/LVTTL clock inputs for redundant clock applica-
tions • CLK0 and CLK1 accepts the following input levels:
LVCMOS/LVTTL
• Output frequency range: 8.33MHz to 125MHz • VCO range: 200MHz to 500MHz • External feedback for ”zero delay” clock regeneration • Cycle-to-cycle jitter: ±100ps (typical) • Output skew: 350ps (maximum) • 3.3V operating supply • -40°C to 85°C ambient operating temperature • Available in lead-free RoHS-compliant package
PIN ASSIGNMENT
52-Lead LQFP
10mm x 10mm x 1.4mm package body Y package Top View
©2016 Integrated Device Technology, Inc
1
Revision E January 26, 2016
BLOCK DIAGRAM
87974I Data Sheet
©2016 Integrated Device Technology, Inc
2
Revision E January 26, 2016
87974I Data Sheet
SIMPLIFIED BLOCK DIAGRAM
CLK_SEL CLK0 CLK1 FB_IN
CLK_EN SEL_A
VCO_SEL
0 1 PLL
PLL_SEL SEL_B
SEL_C
FB_SEL(0:1) nMR/OE
2
0
÷2 0
SEL_A
0 ÷2
DQ
1
÷4 1
1 ÷4
5 QA0:QA4
SEL_B 0 ÷2 1 ÷4
DQ 5
QB0:QB4
SEL_C 0 ÷4 1 ÷6
DQ 4
QC0:QC3
FB_0 FB_1 0 0 ÷4 0 1 ÷6 1 0 ÷8 1 1 ÷12
DQ
QFB
©2016 Integrated Device Technology, Inc
3
Revision E January 26, 2016
87974I Data Sheet
TABLE 1. PIN DESCRIPTIONS
Number
1, 15, 19, 24, 30, 35, 39,
43, 47, 51
Name GND
2 nMR/OE
3 CLK_EN
4 SEL_B 5 SEL_C
6 PLL_SEL
7 SEL_A 8 CLK_SEL 9 CLK0
Type
Description
Power
Power supply ground.
Input
Input Input Input Input Input Input Input
Pullup
Active HIGH outputs enabled (active). When LOW, outputs are disabled (High-impedance state) and reset of the device. During reset/output disable the PLL feedback loop is open and the internal VCO is tied to its lowest frequency. The 87974I requires reset after any loss of PLL lock. Loss of PLL lock may occur when the external feedback path is interrupted. The length of the reset pulse should be greater than one reference clock cycle (CLKx)
Pullup
Synchronizing clock enable. When HIGH, clock outputs QAx:QCx are enabled. When LOW, clock outputs QAx:QCx are low. LVCMOS / LVTTL interface levels.
Pulldown
Selects divide value for Bank B output as described in Table 3D. LVCMOS / LVTTL interface levels.
Pulldown
Selects divide value for Bank C output as described in Table 3D. LVCMOS / LVTTL interface levels.
Pullup
Selects between the PLL and the reference clock as the input to the dividers. When HIGH, selects PLL. When LOW, selects the reference clock. LVCMOS / LVTTL interface levels.
Pulldown
Selects divide value for Bank A output as described in Table 3D. LVCMOS / LVTTL interface levels.
Pulldown
Clock select input. When HIGH, selects CLK1. When LOW, selects CLK0. LVCMOS / LVTTL interface levels.
Pulldown Reference clock input. LVCMOS / LVTTL interface levels.
10
CLK1
Input Pullup Reference clock input. LVCMOS / LVTTL interface levels.
11, 27, 42
nc Unused
No connect.
12 13
14, 20
16, 18, 21, 23, 25
VDD VDDA FB_SEL0, FB_ SEL1
QA4, QA3, QA2, QA1, QA0
Power Power Input
Output
Core supply pin.
Analog supply pin.
Pulldown
Selects divide value for Bank feedback output as described in Table 3E. LVCMOS / LVTTL interface levels.
Bank A clock outputs. 7Ω typical output impedance.
LVCMOS / LVTTL interface levels.
17, 22, 26 28 29
31
32, 34, 36, 38, 40 33, 37, 41
44, 46, 48, 50 45, 49
52
VDDOA VDDOFB QFB
FB_IN
QB4, QB3, QB2, QB1, QB0
VDDOB QC3, QC2, QC1,
QC0 VDDOC
VCO_SEL
Power Power Output
Input
Output Power Output Power Input
Output supply pins for Bank A clock outputs.
Output supply pin for QFB clock output.
Clock output. LVCMOS / LVTTL interface levels.
Feedback input to phase detector for generating clocks with Pullup “zero delay”. Connect to pin 29.
LVCMOS / LVTTL interface levels.
Bank B clock outputs. 7Ω typical output impedance. LVCMOS / LVTTL interface levels.
Output supply pins for Bank B clock outputs.
Bank C clock outputs. 7Ω typical output impedance. LVCMOS / LVTTL interface levels.
Output supply pins for Bank C clock outputs.
Pulldown
Selects VCO ÷ 4 when HIGH. Selects VCO ÷ 2 when LOW. LVCMOS / LVTTL interface levels.
NOTE: and refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Pullup
Pulldown
©2016 In.