9DML0451 Mux Datasheet

9DML0451 Datasheet, PDF, Equivalent


Part Number

9DML0451

Description

2:4 3.3V PCIe Gen1-5 Clock Mux

Manufacture

Renesas

Total Page 11 Pages
Datasheet
Download 9DML0451 Datasheet


9DML0451
2:4 3.3V PCIe Gen1–5 Clock Mux 9DML0441 / 9DML0451
DATASHEET
Description
The 9DML0441 and 9DML0451 devices are 3.3V members of
IDT's Full-Featured PCIe family. They support PCIe Gen1–5
Common Clocked (CC), Separate Reference no Spread
(SRnS), and Separate Reference Independent Spread
(SRIS) architectures. The parts provide a choice of
asynchronous or glitch-free, gapped-clock switching modes,
and offer a choice of integrated output terminations for direct
connection to 85or 100transmission lines.
Typical Applications
Servers
ATE
Storage
Master/Slave applications
Output Features
Four 1–200MHz Low-Power HCSL (LP-HCSL) DIF pairs
9DML0441 default ZOUT = 100
9DML0451 default ZOUT = 85
See AN-891 for easy termination to other logic levels
Features
Direct connection to 100(xx41) or 85(xx51)
transmission lines saves up to 16 resistors
79mW typical power consumption
Spread Spectrum Clocking (SSC) compatible
OE# pins for each output
HCSL-compatible differential inputs
Selectable asynchronous or glitch-free, gapped-clock
switching; allows the mux to be selected at power up even
if both inputs are not running, then transition to glitch-free
switching mode
Space saving 4 × 4 mm 24-VFQFPN
Contact factory for customized versions
Key Specifications
PCIe Gen1–5 CC support
PCIe Gen1–5 SRIS support
Output-to-output skew < 50ps
PCIe Gen5 additive jitter (CC) is < 0.06 ps rms
12kHz–20MHz additive phase jitter 285fs rms typical
at156.25MHz
Block Diagram
^OE(3:0)#
DIF_INA#
DIF_INA
DIF_INB#
DIF_INB
vSW_MODE
^SEL_A_B#
VDDR3.3 x2
4
VDD3.3
A
B
Note: Default resistors are internal on 41/51 devices.
GNDR x2
EPAD/GND
GND
DIF3#
DIF3
DIF2#
DIF2
DIF1#
DIF1
DIF0#
DIF0
9DML0441 / 9DML0451 MAY 22, 2019
1

9DML0451
9DML0441 / 9DML0451 DATASHEET
Pin Configuration
24 23 22 21 20 19
DIF_INA 1
DIF_INA# 2
9DML0441
18 DIF2#
17 DIF2
VDDR3.3 3
9DML0451
16 VDD3.3
VDDR3.3 4 Connect EPAD to 15 GND
DIF_INB 5
GND 14 DIF1#
DIF_INB# 6
13 DIF1
7 8 9 10 11 12
24-VFQFPN, 4 x 4 mm, 0.5mm pitch
^ prefix indicates internal pull-up resistor
v prefix indicates internal pull-down resistor
Power Management Table
OEx# Pin
0
1
DIF_IN
Running
Running
DIFx
True O/P Comp. O/P
Running
Running
Low Low
Power Connections
Pin Number
VDD
GND
3 24
47
16 15
Description
Input A receiver analog
Input B receiver analog
DIF outputs
2:4 3.3V PCIE GEN1–5 CLOCK MUX
2
MAY 22, 2019


Features 2:4 3.3V PCIe Gen1–5 Clock Mux 9DML044 1 / 9DML0451 DATASHEET Description Th e 9DML0441 and 9DML0451 devices are 3.3 V members of IDT's Full-Featured PCIe f amily. They support PCIe Gen1–5 Commo n Clocked (CC), Separate Reference no S pread (SRnS), and Separate Reference In dependent Spread (SRIS) architectures. The parts provide a choice of asynchron ous or glitch-free, gapped-clock switch ing modes, and offer a choice of integr ated output terminations for direct con nection to 85Ω or 100Ω transmission lines. Typical Applications • Server s • ATE • Storage • Master/Slave applications Output Features • Four 1 –200MHz Low-Power HCSL (LP-HCSL) DIF pairs • 9DML0441 default ZOUT = 100 • 9DML0451 default ZOUT = 85 • See AN-891 for easy termination to oth er logic levels Features • Direct co nnection to 100 (xx41) or 85 (xx5 1) transmission lines saves up to 16 re sistors • 79mW typical power consumpt ion • Spread Spectrum Clocking (SSC) compatible • OE# pins for each output • HCSL-compatible differen.
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