70V3589 RAM Datasheet

70V3589 Datasheet, PDF, Equivalent


Part Number

70V3589

Description

HIGH-SPEED 3.3V 128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM

Manufacture

Renesas

Total Page 24 Pages
Datasheet
Download 70V3589 Datasheet


70V3589
HIGH-SPEED 3.3V 128/64K x 36
SYNCHRONOUS DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
70V3599/89S
Features:
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed data access
– Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
– Industrial: 4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 6ns cycle time, 166MHz operation (12Gbps bandwidth)
– Fast 3.6ns clock to data out
– 1.7ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 166MHz
– Data input, address, byte enable and control registers
– Self-timed write allows fast cycle time
Functional Block Diagram
BE3L
BE2L
BE1L
BE0L
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output mode
LVTTL- compatible, 3.3V (±150mV) power supply
for core
LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40°C to +85°C) is
available at 133MHz.
Available in a 208-pin Plastic Quad Flatpack (PQFP),
208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball
Grid Array (BGA)
Supports JTAG features compliant with IEEE 1149.1
Green parts available, see ordering information
BE3R
BE2R
BE1R
BE0R
FT/PIPEL
R/WL
CE0L
CE1L
OEL
1/0 0a 1a
a
0b 1b 0c 1c
bc
0d 1d
d
1
0
1/0
B B BBB B BB
W W WWW W WW
0 1 233 2 10
L L L L R R RR
Dout0-8_L
Dout9-17_L
Dout18-26_L
Dout27-35_L
Dout0-8_R
Dout9-17_R
Dout18-26_R
Dout27-35_R
FT/PIPEL
1d 0d 1c 0c 1b 0b 1a 0a
0/1
abcd
I/O0L - I/O35L
CLKL
A16L(1)
A0L
REPEATL
ADSL
CNTENL
NOTE:
1. A16 is a NC for IDT70V3589.
Counter/
Address
Reg.
TDI
TDO
128K x 36
MEMORY
ARRAY
Din_L
Din_R
ADDR_L
ADDR_R
JTAG
1
1d 0d
d
1c 0c
c
1b 0b
b
1a 0a
1/0
a
1
0
1/0
FT/PIPER
R/WR
CE0R
CE1R
OER
0a 1a 0b 1b 0c 1c 0d 1d
d cb a
0/1
FT/PIPER
Counter/
Address
Reg.
TCK
TMS
TRST
I/O0R - I/O35R
CLKR
A16R(1)
A0R
REPEATR
ADSR
CNTENR
,
5617 tbl 01
NOVEMBER 2019
DSC 5617/13

70V3589
70V3599/89S
High-Speed 3.3V 128/64K x 36 Dual-Port Synchronous Static RAM
Industrial and Commercial Temperature Ranges
Description:
The IDT70V3599/89 is a high-speed 128/64K x 36 bit synchronous
Dual-Port RAM. The memory array utilizes Dual-Port memory cells to
allow simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold
times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times. With an input data register, the
IDT70V3599/89 has been optimized for applications having unidirectional
or bidirectional data flow in bursts. An automatic power down feature,
controlled by CE0 and CE1, permits the on-chip circuitry of each port to
enter a very low standby power mode.
The 70V3599/89 can support an operating voltage of either 3.3V or
2.5V on one or both ports, controllable by the OPT pins. The power supply
for the core of the device (VDD) remains at 3.3V.
Pin Configuration(1,2,3,4,5)
A1 A2 A3 A4
IO19L IO18L VSS TDO
B1 B2 B3 B4
I/O20R VSS I/O18R TDI
A5
NC
B5
NC
A6 A7
A16L(1 A12L
)
B6
B7
A13L A9L
A8
A8L
B8
BE2L
A9 A10
BE1L VDD
B9 B10
CE0L VSS
A11 A12
A13
CLKL CNTENL A4L
B11 B12 B13
ADSL A5L A1L
A14
A0L
B14
VSS
A15 A16 A17
OPTL I/O17L VSS
B15 B16 B17
VDDQR I/O16L I/O15R
C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17
VDDQL I/O19R VDDQR PL/FTL NC A14L A10L BE3L CE1L VSS R/WL A6L A2L VDD I/O16R I/O15L VSS
D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D 1 1 D12 D13 D14 D15 D16 D17
I/O22L VSS I/O21L I/O20L A15L A11L A7L BE0L VDD OEL REPEATL A3L VDD I/O17R VDDQL I/O14L I/O14R
E1 E2 E3 E4
I/O23L I/O22R VDDQR I/O21R
E14 E15 E16 E17
I/O12L I/O13R VSS I/O13L
F1 F2 F3 F4
VDDQL I/O23R I/O24L VSS
F14 F15 F16 F17
VSS I/O12R I/O11L VDDQR
G1 G2 G3 G4
I/O26L VSS I/O25L I/O24R
H1 H2 H3 H4
VDD I/O26R VDDQR I/O25R
J1 J2
VDDQ VDD
L
K1 K2
I/O28R VSS
J3 J4
VSS VSS
K3 K4
I/O27R VSS
L1 L2 L3 L4
I/O29R I/O28L VDDQR I/O27L
70V3599/89
BF208(6)
BFG208(6)
208-Pin fpBGA
Top View(7)
G14 G15 G16 G17
I/O9L VDDQL I/O10L I/O11R
H14 H15 H16 H17
VDD IO9R VSS I/O10R
J14 J15 J16 J17
VSS VDD VSS VDDQR
K14 K15 K16 K17
I/O7R VDDQ I/O8R VSS
L
L14 L15 L16 L17
I/O6R I/O7L VSS I/O8L
M1 M2 M3 M4
VDDQL I/O29L I/O30R VSS
M14 M15 M16 M17
VSS I/O6L I/O5R VDDQR
N1 N2 N3 N4
I/O31L VSS I/O31R I/O30L
N14 N15 N16 N17
I/O3R VDDQL I/O4R I/O5L
P1 P2 P3 P4 P5 P6 P7 P8 P9 P10
I/O32R I/O32L VDDQR I/O35R TRST A16R(1) A12R A8R BE1R VDD
R1 R2 R3 R4 R5 R6 R7 R8 R9 R10
VSS I/O33L I/O34R TCK NC A13R A9R BE2R CE0R VSS
P11 P12 P13
CLKR CNTEN A4R
R
R11 R12 R13
ADSR A5R A1R
P14 P15 P16 P17
I/O2L I/O3L VSS I/O4L
R14 R15 R16 R17
VSS VDDQL I/O1R VDDQR
T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17
I/O33R I/O34L VDDQL TMS NC A14R A10R BE3R CE1R VSS R/WR A6R A2R VSS I/O0R VSS I/O2R
U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17
VSS I/O35L PL/FTR NC A15R A11R A7R BE0R VDD OER REPEATR A3R A0R VDD OPTR I/O0L I/O1L
NOTES:
5617 drw 02c
1. A16 is a NC for IDT70V3589.
2. All VDD pins must be connected to 3.3V power supply.
3. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V).
4. All VSS pins must be connected to ground supply.
5. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.
62.42
,


Features HIGH-SPEED 3.3V 128/64K x 36 SYNCHRONOUS DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE 70V3599/89S Features: ◆ True Dual-Port memory cells which allow simultaneous access of the same memory location ◆ High-speed data access Commercial: 3.6ns (166MHz)/4.2ns (133 MHz) (max.) – Industrial: 4.2ns (133M Hz) (max.) ◆ Selectable Pipelined or Flow-Through output mode ◆ Counter en able and repeat features ◆ Dual chip enables allow for depth expansion witho ut additional logic ◆ Full synchronou s operation on both ports – 6ns cycle time, 166MHz operation (12Gbps bandwid th) – Fast 3.6ns clock to data out 1.7ns setup to clock and 0.5ns hold o n all control, data, and address inputs @ 166MHz – Data input, address, byte enable and control registers – Self- timed write allows fast cycle time Func tional Block Diagram BE3L BE2L BE1L BE0 L ◆ Separate byte controls for multi plexed bus and bus matching compatibili ty ◆ Dual Cycle Deselect (DCD) for Pipelined Output mode ◆ LVTTL- compatible, 3.3V (±150mV).
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