9FGV0631C Generator Datasheet

9FGV0631C Datasheet, PDF, Equivalent


Part Number

9FGV0631C

Description

6-Output Very Low-Power PCIe Gen 1-2-3-4 Clock Generator

Manufacture

Renesas

Total Page 17 Pages
Datasheet
Download 9FGV0631C Datasheet


9FGV0631C
6-Output Very Low-Power PCIe Gen 1-2-3-4
Clock Generator
9FGV0631C
DATASHEET
Description
The 9FGV0631C is a member of IDT's SOC-Friendly 1.8V
very low-power PCIe clock family. The device has 6 output
enables for clock management, 2 different spread spectrum
levels in addition to spread off, and 2 selectable SMBus
addresses.
Typical Applications
PCIe Gen1–4 clock generation for Riser Cards, Storage,
Networking, JBOD, Communications, Access Points
Output Features
6 100MHz Low-Power (LP) HCSL DIF pairs
1 1.8V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF phase jitter is PCIe Gen1-2-3-4 compliant
REF phase jitter is < 1.5ps RMS
Block Diagram
Features
LP-HCSL outputs; save 12 resistors compared to standard
PCIe devices
54mW typical power consumption; reduced thermal
concerns
Outputs can optionally be supplied from any voltage
between 1.05V and 1.8V; maximum power savings
OE# pins; support DIF power management
Programmable slew rate for each output; allows tuning for
various line lengths
Programmable output amplitude; allows tuning for various
application environments
DIF outputs blocked until PLL is locked; clean system
start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
3.3V tolerant SMBus interface works with legacy controllers
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
Space saving 5 x 5 mm 40-VFQFPN; minimal board space
vOE(5:0)#
XIN/CLKIN_25
X2
OSC
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
SS Capable PLL
REF1.8
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9FGV0631C JUNE 6, 2019
1

9FGV0631C
9FGV0631C DATASHEET
Pin Configuration
40 39 38 37 36 35 34 33 32 31
vSS_EN_tri 1
30 vOE3#
X1_25 2
29 DIF3#
X2 3
28 DIF3
VDDXTAL1.8 4
VDDREF1.8 5
vSADR/REF1.8 6
9FGV0631C
Paddle is GND
27 VDDIO
26 VDDA1.8
25 NC
NC 7
24 vOE2#
GNDDIG 8
23 DIF2#
SCLK_3.3 9
22 DIF2
SDATA_3.3 10
21 vOE1#
11 12 13 14 15 16 17 18 19 20
SMBus Address Selection Table
State of SADR on first application
of CKPWRGD_PD#
SADR
0
1
40-VFQFPN, 5 x 5 mm, 0.4mm pitch
v prefix indicates internal 120kOhm pull-down resistor
^ prefix indicates internal 120kOhm pull-up resistor
Address
1101000
1101010
+ Read/Write Bit
x
x
Power Management Table
CKPWRGD_PD#
SMBus
OE bit
OEx#
DIFx
True O/P
Comp. O/P REF
0 X X Low Low Hi-Z1
1
1
0
Running
Running Running
1 0 1 Low Low Low
1. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when
CKPWRG_PD# is low, REF is Low.
Power Connections
Pin Number
VDD
4
5
VDDIO
11
12,17,27,32,39
26
GND
41
41
8
41
41
Description
XTAL OSC
REF Power
Digital (dirty)
Power
DIF outputs
PLL Analog
6-OUTPUT VERY LOW-POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
2
JUNE 6, 2019


Features 6-Output Very Low-Power PCIe Gen 1-2-3-4 Clock Generator 9FGV0631C DATASHEET Description The 9FGV0631C is a member o f IDT's SOC-Friendly 1.8V very low-powe r PCIe clock family. The device has 6 o utput enables for clock management, 2 d ifferent spread spectrum levels in addi tion to spread off, and 2 selectable SM Bus addresses. Typical Applications PCI e Gen1–4 clock generation for Riser C ards, Storage, Networking, JBOD, Commun ications, Access Points Output Features • 6 100MHz Low-Power (LP) HCSL DIF p airs • 1 1.8V LVCMOS REF output w/Wak e-On-LAN (WOL) support Key Specificatio ns • DIF cycle-to-cycle jitter <50ps • DIF output-to-output skew <50ps • DIF phase jitter is PCIe Gen1-2-3-4 co mpliant • REF phase jitter is < 1.5ps RMS Block Diagram Features • LP-HCS L outputs; save 12 resistors compared t o standard PCIe devices • 54mW typica l power consumption; reduced thermal co ncerns • Outputs can optionally be su pplied from any voltage between 1.05V and 1.8V; maximum power savings • OE# pins; s.
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