CY14MC256J nvSRAM Datasheet

CY14MC256J Datasheet, PDF, Equivalent


Part Number

CY14MC256J

Description

256-Kbit (32 K 8) Serial (I2C) nvSRAM

Manufacture

Cypress

Total Page 30 Pages
Datasheet
Download CY14MC256J Datasheet


CY14MC256J
CY14MC256J
CY14MB256J
CY14ME256J
256-Kbit (32 K × 8) Serial (I2C) nvSRAM
256-Kbit (32 K × 8) Serial (I2C) nvSRAM
Features
256-Kbit nonvolatile static random access memory (nvSRAM)
Internally organized as 32 K × 8
STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by using I2C
command (Software STORE) or HSB pin (Hardware STORE)
RECALL
RECALL)
to
or
SRAM initiated on power-up (Power-Up
by I2C command (Software RECALL)
Automatic STORE on power-down with a small capacitor
(except for CY14MX256J1)
High reliability
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
Data retention: 20 years at 85 C
High speed I2C interface[1]
Industry standard 100 kHz and 400 kHz speed
Fast-mode Plus: 1 MHz speed
High speed: 3.4 MHz
Zero cycle delay reads and writes
Write protection
Hardware protection using Write Protect (WP) pin
Software block protection for one quarter, half, or entire array
I2C access to special functions
Nonvolatile STORE/RECALL
8 byte serial number
Manufacturer ID and Product ID
Sleep mode
Low power consumption
Average active current of 1 mA at 3.4-MHz operation
Average standby mode current of 150 µA
Sleep mode current of 8 µA
Industry standard configurations
Operating voltages:
• CY14MC256J: VCC = 2.4 V to 2.6 V
• CY14MB256J: VCC = 2.7 V to 3.6 V
• CY14ME256J: VCC = 4.5 V to 5.5 V
Industrial temperature
8- and 16-pin small outline integrated circuit (SOIC) package
Restriction of hazardous substances (RoHS) compliant
Overview
The Cypress CY14MC256J/CY14MB256J/CY14ME256J
combines a 256-Kbit nvSRAM[2] with a nonvolatile element in
each memory cell. The memory is organized as 32 K words of
8 bits each. The embedded nonvolatile elements incorporate the
QuantumTrap technology, creating the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while the QuantumTrap cells provide highly reliable
nonvolatile storage of data. Data transfers from SRAM to the
nonvolatile elements (STORE operation) takes place
automatically at power-down (except for CY14MX256J1). On
power-up, data is restored to the SRAM from the nonvolatile
memory (RECALL operation). The STORE and RECALL
operations can also be initiated by the user through I2C
commands.
For a complete list of related documentation, click here.
Configuration
Feature
AutoStore
Software
STORE
Hardware
STORE
Slave Address
pins
CY14MX256J1 CY14MX256J2 CY14MX256J3
No Yes Yes
Yes Yes Yes
No No Yes
A2, A1, A0
A2, A1
A2, A1, A0
Logic Block Diagram
VCC VCAP
Serial Number
8x8
Manufacturer ID /
Product ID
Power Control
Block
Sleep
Memory Control Register
Command Register
QuantumTrap
32 K x 8
SDA
SCL
A2, A1, A0
WP
2
I C Control Logic
Slave Address
Decoder
Control Registers Slave
Memory Slave
Memory
Address and Data
Control
SRAM
32 K x 8
STORE
RECALL
Notes
1. The I2C nvSRAM is a single solution which is usable for all four speed modes of operation. As a result, some I/O parameters are slightly different than those on chips
which support only one mode of operation. Refer to AN87209 for more details.
2. Serial (I2C) nvSRAM is referred to as nvSRAM throughout the datasheet.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-65233 Rev. *I
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 26, 2014

CY14MC256J
CY14MC256J
CY14MB256J
CY14ME256J
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
I2C Interface ...................................................................... 4
Protocol Overview ............................................................ 4
I2C Protocol – Data Transfer ....................................... 4
Data Validity ................................................................ 5
START Condition (S) ................................................... 5
STOP Condition (P) ..................................................... 5
Repeated START (Sr) ................................................. 5
Byte Format ................................................................. 5
Acknowledge / No-acknowledge ................................. 5
High Speed Mode (Hs-mode) ...................................... 6
Slave Device Address ................................................. 7
Write Protection (WP) .................................................. 9
AutoStore Operation .................................................... 9
Hardware STORE and HSB pin Operation ................. 9
Hardware RECALL (Power-Up) .................................. 9
Write Operation ......................................................... 10
Read Operation ......................................................... 10
Memory Slave Access ............................................... 10
Control Registers Slave ............................................. 14
Serial Number ................................................................. 16
Serial Number Write .................................................. 16
Serial Number Lock ................................................... 16
Serial Number Read .................................................. 16
Device ID ......................................................................... 17
Executing Commands Using Command Register ..... 17
Maximum Ratings ........................................................... 18
Operating Range ............................................................. 18
DC Electrical Characteristics ........................................ 18
Data Retention and Endurance ..................................... 19
Thermal Resistance ........................................................ 19
AC Test Loads and Waveforms ..................................... 20
AC Test Conditions ........................................................ 20
AC Switching Characteristics ....................................... 21
Switching Waveforms .................................................... 21
nvSRAM Specifications ................................................. 22
Switching Waveforms .................................................... 22
Software Controlled STORE/RECALL Cycles .............. 23
Switching Waveforms .................................................... 23
Hardware STORE Cycle ................................................. 24
Switching Waveforms .................................................... 24
Ordering Information ...................................................... 25
Ordering Code Definitions ......................................... 25
Package Diagrams .......................................................... 26
Acronyms ........................................................................ 28
Document Conventions ................................................. 28
Units of Measure ....................................................... 28
Document History Page ................................................. 29
Sales, Solutions, and Legal Information ...................... 30
Worldwide Sales and Design Support ....................... 30
Products .................................................................... 30
PSoC® Solutions ...................................................... 30
Cypress Developer Community ................................. 30
Technical Support ..................................................... 30
Document Number: 001-65233 Rev. *I
Page 2 of 30


Features CY14MC256J CY14MB256J CY14ME256J 256-Kbi t (32 K × 8) Serial (I2C) nvSRAM 256- Kbit (32 K × 8) Serial (I2C) nvSRAM Fe atures ■ 256-Kbit nonvolatile static random access memory (nvSRAM) ❐ Int ernally organized as 32 K × 8 ❐ STOR E to QuantumTrap nonvolatile elements i nitiated automatically on power-down (A utoStore) or by using I2C command (Sof tware STORE) or HSB pin (Hardware STORE ) ❐ RECALL RECALL) to or SRAM ini tiated on power-up (Power-Up by I2C com mand (Software RECALL) ❐ Automatic S TORE on power-down with a small capacit or (except for CY14MX256J1) ■ High r eliability ❐ Infinite read, write, an d RECALL cycles ❐ 1 million STORE cyc les to QuantumTrap ❐ Data retention: 20 years at 85 C ■ High speed I2C interface[1] ❐ Industry standard 100 kHz and 400 kHz speed ❐ Fast-mode Plu s: 1 MHz speed ❐ High speed: 3.4 MHz ❐ Zero cycle delay reads and writes ■ Write protection ❐ Hardware prote ction using Write Protect (WP) pin ❐ Software block protection for one quarter, half, or entire arra.
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