R2J20658BNP MOSFET Datasheet

R2J20658BNP Datasheet, PDF, Equivalent


Part Number

R2J20658BNP

Description

Integrated Driver - MOSFET

Manufacture

Renesas

Total Page 16 Pages
Datasheet
Download R2J20658BNP Datasheet


R2J20658BNP
Preliminary Datasheet
R2J20658BNP
Integrated Driver - MOS FET (DrMOS)
R07DS0550EJ0101
(Previous No.: R07DS0542EJ0100)
Rev.1.01
Sep 30, 2011
Description
The R2J20658BNP multi-chip module incorporates a high-side MOS FET, low-side MOS FET, and MOS-FET driver
in a single QFN package. The on and off timing of the power MOS FET is optimized by the built-in driver, making this
device suitable for large-current buck converters. The chip also incorporates a high-side bootstrap switch, eliminating
the need for an external SBD for this purpose.
Features
Based on Intel 6 6 DrMOS Specification.
Built-in power MOS FET suitable for Desktop, Server application.
Low-side MOS FET with built-in SBD for lower loss and reduced ringing.
Built-in driver circuit which matches the power MOS FET
Built-in tri-state input function which can support a number of PWM controllers
High-frequency operation (above 1 MHz) possible
VIN operating-voltage range: 20 Vmax
Large average output current (Max.40 A)
Achieve low power dissipation
Controllable driver: Remote on/off
Support Mid-Voltage PWM signal to enter zero current detection
Double thermal protection: Thermal Warning & Thermal Shutdown
Built-in bootstrapping Switch
Small package: QFN40 (6 mm 6 mm 0.95 mm)
Pb-free/Halogen-free
Outline
THWN
DISBL#
LSDBL#
PWM
Integrated Driver-MOS FET (DrMOS)
QFN40 package 6 mm × 6 mm
VCIN Reg5V BOOT GH VIN
1
40
Driver
Pad
10
High-side
MOS Pad
11
MOS FET Driver
VSWH
Low-side MOS Pad
CGND
GL PGND
31
30
(Bottom view)
20
21
R07DS0550EJ0101 Rev.1.01
Sep 30, 2011
Page 1 of 15

R2J20658BNP
R2J20658BNP
Block Diagram
VCIN Reg5V
BOOT GH
Driver Chip
Preliminary
THWN
DISBL#
LSDBL#
PWM
THWN
2 μA
CGND
THDN
UVL
Reg5V
Supervisor
Boot
SW
CGND Reg5V
Level Shifter
160 k
20 k
Zero
Current
Det.
Reg5V
Input Logic
(TTL Level)
(3 state in)
3 state signal
Overlap
Protection.
& Logic
3 state signal
Reg5V
35 k
VIN
High-side
MOS FET
VSWH
Low-side
MOS FET
PGND
CGND
Notes: 1. Truth table for the DISBL# pin
DISBL# Input
Driver Chip Status
"L" Shutdown (GL, GH = "L")
"Open"
Shutdown (GL, GH = "L")
"H" Enable (GL, GH = "Active")
3. Output signal from the UVL block
UVL output
Logic Level
"H"
For shutdown
"L"
VL
For active
VCIN
VH
5. Truth table for the THDN block
Driver IC Temp.
Driver Chip Status
< 150°C
Enable (GL, GH = "Active")
> 150°C
Shutdown (GL, GH = "L")
(latch-off)
GL
2. Truth table for the LSDBL# pin
LSDBL#
Input
PWM
Input
GL Status
"L" *
"L"
"Open" "L" or "H" "Continuous
or "H"
Conduction Mode"
"Open" "Zero Current
or "Mid" Detection" Mode
4. Output signal from the THWN block
"H"
Thermal Warning
Logic Level
"L"
Normal
operating
Thermal
Warning
TIC(°C)
TwarnL TwarnH
R07DS0550EJ0101 Rev.1.01
Sep 30, 2011
Page 2 of 15


Features Preliminary Datasheet R2J20658BNP Integ rated Driver - MOS FET (DrMOS) R07DS05 50EJ0101 (Previous No.: R07DS0542EJ0100 ) Rev.1.01 Sep 30, 2011 Description Th e R2J20658BNP multi-chip module incorpo rates a high-side MOS FET, low-side MOS FET, and MOS-FET driver in a single QF N package. The on and off timing of the power MOS FET is optimized by the buil t-in driver, making this device suitabl e for large-current buck converters. Th e chip also incorporates a high-side bo otstrap switch, eliminating the need fo r an external SBD for this purpose. Fea tures  Based on Intel 6  6 DrMOS Specification.  Built-in power MOS F ET suitable for Desktop, Server applica tion.  Low-side MOS FET with built-i n SBD for lower loss and reduced ringin g.  Built-in driver circuit which ma tches the power MOS FET  Built-in tr i-state input function which can suppor t a number of PWM controllers  High- frequency operation (above 1 MHz) possi ble  VIN operating-voltage range: 20 Vmax  Large average output current (Ma.
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