82C88 Controller Datasheet

82C88 Datasheet, PDF, Equivalent


Part Number

82C88

Description

CMOS Bus Controller

Manufacture

Renesas

Total Page 12 Pages
Datasheet
Download 82C88 Datasheet


82C88
82C88
CMOS Bus Controller
The Intersil 82C88 is a high performance CMOS Bus
Controller manufactured using a self-aligned silicon gate
CMOS process (Scaled SAJI IV). The 82C88 provides the
control and command timing signals for 80C86, 80C88,
8086, 8088, 8089, 80186, and 80188 based systems. The
high output drive capability of the 82C88 eliminates the need
for additional bus drivers.
Static CMOS circuit design insures low operating power. The
Intersil advanced SAJI process results in performance equal
to or greater than existing equivalent products at a significant
power savings.
Pinouts
20 LD PDIP, CERDIP
TOP VIEW
IOB 1
CLK 2
S1 3
DT/ R 4
ALE 5
AEN 6
MRDC 7
AMWC 8
MWTC 9
GND 10
20 VCC
19 S0
18 S2
17 MCE/PDEN
16 DEN
15 CEN
14 INTA
13 IORC
12 AIOWC
11 IOWC
20 LD PLCC, CLCC
TOP VIEW
3 2 1 20 19
DT/ R 4
ALE 5
AEN 6
MRDC 7
18 S2
17 MCE/PDEN
16 DEN
15 CEN
AMWC 8
14 INTA
9 10 11 12 13
DATASHEET
FN2979
Rev 3.00
August 13, 2015
Features
• Compatible with Bipolar 8288
• Performance Compatible with:
- 80C86/80C88 . . . . . . . . . . . . . . . . . . . . . . . . . (5/8MHz)
- 80186/80188. . . . . . . . . . . . . . . . . . . . . . . . . . (6/8MHz)
- 8086/8088. . . . . . . . . . . . . . . . . . . . . . . . . . . . (5/8MHz)
- 8089
• Provides Advanced Commands for Multi-Master Busses
• Three-State Command Outputs
• Bipolar Drive Capability
• Scaled SAJI IV CMOS Process
• Single 5V Power Supply
• Low Power Operation
- ICCSB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10A (Max)
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . 1mA/MHz (Max)
• Operating Temperature Ranges
- C82C88 . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
- I82C88 . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
- M82C88 . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
• Pb-Free Plus Anneal Available (RoHS Compliant)
Ordering Information
PART NUMBER
TEMP
PART
RANGE PKG.
MARKING PACKAGE (°C) DWG. #
CP82C88Z (Note) (No CP82C88Z 20 Ld PDIP
longer available or
(Pb-free)
supported)
0 to +70
E20.3
CS82C88
CS82C88
(No longer available
or supported)
20 Ld
PLCC
0 to +70 N20.35
MR82C88/B
MR82C88/B 20 Pad
No longer available
CLCC
or supported)
-55 to +125 J20.A
MD82C88/B
MD82C88/B 20 Ld
-55 to +125 F20.3
CERDIP
8406901RA
8406901RA SMD#
F20.3
NOTE: Intersil Pb-free plus anneal products employ special Pb-free
material sets; molding compounds/die attach materials and 100% matte
tin plate termination finish, which are RoHS compliant and compatible
with both SnPb and Pb-free soldering operations. Intersil Pb-free
products are MSL classified at Pb-free peak reflow temperatures that
meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
FN2979 Rev 3.00
August 13, 2015
Page 1 of 12

82C88
82C88
Functional Diagram
S0
S1
S2
CONTROL
INPUT
CLK
AEN
CEN
IOB
STATUS
DECODER
CONTROL
LOGIC
VCC
COMMAND
SIGNAL
GENERATOR
CONTROL
SIGNAL
GENERATOR
MRDC
MWTC
AMWC
IORC
IOWC
AIOWC
INTA
DT/R
DEN
MCE/PDEN
ALE
MULTIBUSTM
COMMAND
SIGNALS
ADDRESS LATCH,
DATA TRANSCEIVER,
AND INTERRUPT
CONTROL SIGNALS
GND
Pin Description
PIN
SYMBOL NUMBER TYPE
DESCRIPTION
VCC
GND
20
10
VCC: The +5V power supply pin. A 0.1F capacitor between pins 10 and 20 is recommended for decoupling.
GROUND.
S0, S1, S2 19, 3, 18
I STATUS INPUT PINS: These pins are the input pins from the 80C86, 80C88,8086/88, 8089 processors. The
82C88 decodes these inputs to generate command and control signals at the appropriate time. When Status pins
are not in use (passive), command outputs are held HIGH (See Table1).
CLK 2 I CLOCK: This is a CMOS compatible input which receives a clock signal from the 82C84A or 82C85 clock
generator and serves to establish when command/control signals are generated.
ALE 5 O ADDRESS LATCH ENABLE: This signal serves to strobe an address into the address latches. This signal is
active HIGH and latching occurs on the falling (HIGH to LOW) transition. ALE is intended for use with transparent
D type latches, such as the 82C82 and 82C83H.
DEN
16 O DATA ENABLE: This signal serves to enable data transceivers onto either the local or system data bus. This
signal is active HIGH.
DT/R
4 O DATA TRANSMIT/RECEIVE: This signal establishes the direction of data flow through the transceivers. A HIGH
on this line indicates Transmit (write to I/O or memory) and a LOW indicates Receive (read from I/O or memory).
AEN 6 I ADDRESS ENABLE: AEN enables command outputs of the 82C88 Bus Controller a minimum of 110ns (250ns
maximum) after it becomes active (LOW). AEN going inactive immediately three-states the command output
drivers. AEN does not affect the I/O command lines if the 82C88 is in the I/O Bus mode (IOB tied HIGH).
CEN 15 I COMMAND ENABLE: When this signal is LOW all 82C88 command outputs and the DEN and PDEN control
outputs are forced to their Inactive state. When this signal is HIGH, these same outputs are enabled.
IOB 1 I INPUT/OUTPUT BUS MODE: When the IOB pin is strapped HIGH, the 82C88 functions in the I/O Bus mode.
When it is strapped LOW, the 82C88 functions in the System Bus mode (See I/O Bus and System Bus sections).
AIOWC
12
O ADVANCED I/O WRITE COMMAND: The AIOWC issues an I/O Write Command earlier in the machine cycle to
give I/O devices an early indication of a write instruction. Its timing is the same as a read command signal.
AIOWC is active LOW.
IOWC 11 O I/O WRITE COMMAND: This command line instructs an I/O device to read the data on the data bus. The signal
is active LOW.
IORC 13 O I/O READ COMMAND: This command line instructs an I/O device to drive its data onto the data bus. This signal
is active LOW.
FN2979 Rev 3.00
August 13, 2015
Page 2 of 12


Features MWTC GND IOWC AIOWC IORC 82C88 CMOS Bus Controller The Intersil 82C88 is a hi gh performance CMOS Bus Controller manu factured using a self-aligned silicon g ate CMOS process (Scaled SAJI IV). The 82C88 provides the control and command timing signals for 80C86, 80C88, 8086, 8088, 8089, 80186, and 80188 based syst ems. The high output drive capability o f the 82C88 eliminates the need for add itional bus drivers. Static CMOS circui t design insures low operating power. T he Intersil advanced SAJI process resul ts in performance equal to or greater t han existing equivalent products at a s ignificant power savings. Pinouts 20 LD PDIP, CERDIP TOP VIEW IOB 1 CLK 2 S 1 3 DT/ R 4 ALE 5 AEN 6 MRDC 7 AMWC 8 M WTC 9 GND 10 20 VCC 19 S0 18 S2 17 MCE /PDEN 16 DEN 15 CEN 14 INTA 13 IORC 12 AIOWC 11 IOWC 20 LD PLCC, CLCC TOP VIE W S1 CLK IOB VCC S0 3 2 1 20 19 DT/ R 4 ALE 5 AEN 6 MRDC 7 18 S2 17 MCE/PD EN 16 DEN 15 CEN AMWC 8 14 INTA 9 10 11 12 13 DATASHEET FN2979 Rev 3.00 August 13, 2015 Features .
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