ICS9DB803D BUFFER Datasheet

ICS9DB803D Datasheet, PDF, Equivalent


Part Number

ICS9DB803D

Description

EIGHT OUTPUT DIFFERENTIAL BUFFER

Manufacture

Renesas

Total Page 23 Pages
Datasheet
Download ICS9DB803D Datasheet


ICS9DB803D
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2
DATASHEET
ICS9DB803D
General Description
The ICS9DB803D is compatible with the Intel DB800v2
Differential Buffer Specification. This buffer provides 8
PCI-Express Gen2 clocks. The ICS9DB803D is driven by a
differential output pair from a CK410B+, CK505 or CK509B
main clock generator.
Recommended Application
DB800v2 compatible part with PCIe Gen1 and Gen2
Support
Output Features
8 - 0.7V current-mode differential output pairs
Supports zero delay buffer mode and fanout mode
Bandwidth programming available
50-100 MHz operation in PLL mode
50-400 MHz operation in Bypass mode
Features/Benefits
Spread spectrum modulation tolerant, 0 to -0.5% down
spread and +/- 0.25% center spread
Supports undriven differential outputs in PD# and
SRC_STOP# modes for power management
Key Specifications
Outputs cycle-cycle jitter < 50ps
Output to Output skew <50ps
Phase jitter: PCIe Gen1 < 86ps peak to peak
Phase jitter: PCIe Gen2 < 3.0/3.1ps rms
Functional Block Diagram
OE _ (7 : 0 )
8
SRC _IN
SRC _IN #
SPR EAD
C OM PAT IBLE
PLL
M
U
X
ST OP
L O GI C
8
D IF(7:0))
SRC _ST OP#
H IGH _BW #
B YP A S S # / PL L
PD#
SDAT A
SCLK
C ON T R OL
LOGIC
I RE F
LOC K
Note: Polarities shown are for OE_INV=0.
IDT® EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2
1
ICS9DB803D
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ICS9DB803D
ICS9DB803D
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2
Pin Configuration
SRC_DIV# 1
48 VDDA
VDDR 2
47 GNDA
GND 3
46 IREF
SRC_IN 4
45 LOCK
SRC_IN# 5
44 OE_7
OE_0 6
43 OE_4
OE_3 7
42 DIF_7
DIF_0 8
41 DIF_7#
DIF_0# 9
40 OE_INV
GND 10
39 VDD
VDD 11
38 DIF_6
DIF_1 12
37 DIF_6#
DIF_1# 13
36 OE_6
OE_1 14
35 OE_5
OE_2 15
34 DIF_5
DIF_2 16
33 DIF_5#
DIF_2# 17
32 GND
GND 18
31 VDD
VDD 19
30 DIF_4
DIF_3 20
29 DIF_4#
DIF_3# 21
28 HIGH_BW#
BYPASS#/PLL 22
27 DIF_STOP#
SCLK 23
26 PD#
SDATA 24
25 GND
OE_INV = 0
SRC_DIV# 1
48 VDDA
VDDR 2
47 GNDA
GND 3
46 IREF
SRC_IN 4
45 LOCK
SRC_IN# 5
44 OE7#
OE0# 6
43 OE4#
OE3# 7
42 DIF_7
DIF_0 8
41 DIF_7#
DIF_0# 9
40 OE_INV
GND 10
39 VDD
VDD 11
38 DIF_6
DIF_1 12
37 DIF_6#
DIF_1# 13
36 OE6#
OE1# 14
35 OE5#
OE2# 15
34 DIF_5
DIF_2 16
33 DIF_5#
DIF_2# 17
32 GND
GND 18
31 VDD
VDD 19
30 DIF_4
DIF_3 20
29 DIF_4#
DIF_3# 21
28 HIGH_BW#
BYPASS#/PLL 22
27 DIF_STOP
SCLK 23
26 PD
SDATA 24
25 GND
OE_INV = 1
Power Groups
Pin Number
VDD
GND
23
6,11,19,
31,39
10,18, 25,32
N/A 47
48 47
Description
SRC_IN/SRC_IN#
DIF(7:0)
IREF
Analog VDD & GND for PLL core
Polarity Inversion Pin List Table
Pins
6
7
14
15
26
27
35
36
43
44
OE_INV
01
OE_0
OE_0#
OE_3
OE_3#
OE_1
OE_1#
OE_2
OE_2#
PD# PD
DIF_STOP# DIF_STOP
OE_5
OE_5#
OE_6
OE_6#
OE_4
OE_4#
OE_7
OE_7#
IDT® EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1 AND GEN2
2
ICS9DB803D
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Features EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCI E GEN1 AND GEN2 DATASHEET ICS9DB803D General Description The ICS9DB803D is c ompatible with the Intel DB800v2 Differ ential Buffer Specification. This buffe r provides 8 PCI-Express Gen2 clocks. T he ICS9DB803D is driven by a differenti al output pair from a CK410B+, CK505 or CK509B main clock generator. Recommend ed Application DB800v2 compatible part with PCIe Gen1 and Gen2 Support Output Features • 8 - 0.7V current-mode diff erential output pairs • Supports zero delay buffer mode and fanout mode • Bandwidth programming available • 50- 100 MHz operation in PLL mode • 50-40 0 MHz operation in Bypass mode Feature s/Benefits • Spread spectrum modulati on tolerant, 0 to -0.5% down spread and +/- 0.25% center spread • Supports u ndriven differential outputs in PD# and SRC_STOP# modes for power management K ey Specifications • Outputs cycle-cyc le jitter < 50ps • Output to Output s kew <50ps • Phase jitter: PCIe Gen1 < 86ps peak to peak • Phase jitter: PCIe Gen2.
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