ICS9DB102

Two Output Differential Buffer for PCIe Gen1 & Gen2 DATASHEET ICS9DB102 Description The ICS9DB102 zero-delay buffer supports PCI Express clocking requirements. The ICS9DB102 is driven by a differential SRC output pair from an ICS CK410/CK505-compliant main clock. It attenuates jitter on the input clock and has a selectable PLL Band Width to maximize performance in systems with or without Spread-Spectrum clocking. Output Features 2 - 0.7V current mode differential output pairs (HCSL) Features/Benefits CLKREQ# pin for outputs 1 and 4/output enable for Express Card applications PLL or bypass mode/PLL can dejitter incoming clock Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL’s Spread Spectrum Compatible/tracks spreading input clock for low EMI SMBus Interface/unused outputs can be disabled Industrial temperature range available Key Specifications Cycle-to-cycle jitter < 35ps Output-to-output skew < 25ps Functional Block Diagram CLKREQ0# CLKREQ1# CLK_INT C LK_IN C PLL_BW SMBDAT SMBCLK SPREAD COMPATIBLE PLL CONTROL LOGIC PCIEX0 PCIEX1 IREF IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2 1 852 REV Q 08/27/13 ICS9DB102 Two Output Differential Buffer for PCIe Gen1 & Gen2 Pin Configuration PLL_BW 1 CLK_INT 2 CLK_INC 3 vCLKREQ0# 4 VDD 5 GND 6 PCIEXT0 7 PCIEXC0 8 VDD 9 SMBDAT 10 ICS9DB102 20 VDDA 19 GNDA 18 IREF 17 vCLKREQ1# 16 VDD 15 GND 14 PCIEXT1 13 PCIEXC1 12 VDD 11 SMBCLK Note: Pins preceeded by ' v ' have internal 120K o...