ICS9DB102 Buffer Datasheet

ICS9DB102 Datasheet, PDF, Equivalent


Part Number

ICS9DB102

Description

Two Output Differential Buffer

Manufacture

Renesas

Total Page 14 Pages
Datasheet
Download ICS9DB102 Datasheet


ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
DATASHEET
ICS9DB102
Description
The ICS9DB102 zero-delay buffer supports PCI Express
clocking requirements. The ICS9DB102 is driven by a differential
SRC output pair from an ICS CK410/CK505-compliant main
clock. It attenuates jitter on the input clock and has a selectable
PLL Band Width to maximize performance in systems with or
without Spread-Spectrum clocking.
Output Features
• 2 - 0.7V current mode differential output pairs (HCSL)
Features/Benefits
• CLKREQ# pin for outputs 1 and 4/output enable for Express
Card applications
• PLL or bypass mode/PLL can dejitter incoming clock
• Selectable PLL bandwidth/minimizes jitter peaking in
downstream PLL’s
• Spread Spectrum Compatible/tracks spreading input clock
for low EMI
• SMBus Interface/unused outputs can be disabled
• Industrial temperature range available
Key Specifications
• Cycle-to-cycle jitter < 35ps
• Output-to-output skew < 25ps
Functional Block Diagram
CLKREQ0#
CLKREQ1#
CLK_INT
C LK_IN C
PLL_BW
SMBDAT
SMBCLK
SPREAD
COMPATIBLE
PLL
CONTROL
LOGIC
PCIEX0
PCIEX1
IREF
IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2
1
852 REV Q 08/27/13

ICS9DB102
ICS9DB102
Two Output Differential Buffer for PCIe Gen1 & Gen2
Pin Configuration
PLL_BW 1
CLK_INT 2
CLK_INC 3
vCLKREQ0# 4
VDD 5
GND 6
PCIEXT0 7
PCIEXC0 8
VDD 9
SMBDAT 10
20 VDDA
19 GNDA
18 IREF
17 vCLKREQ1#
16 VDD
15 GND
14 PCIEXT1
13 PCIEXC1
12 VDD
11 SMBCLK
Note: Pins preceeded by ' v ' have internal
120K ohm pull down resistors
Power Groups
Pin Number
VDD
GND
5,9,12,16
6,15
96
20 19
20 19
Description
PCI Express Outputs
SMBUS
IREF
Analog VDD & GND for PLL core
20-pin SSOP & TSSOP
Pin Description
PIN #
PIN NAME
1 PLL_BW
2 CLK_INT
3 CLK_INC
4 vCLKREQ0#
5 VDD
6 GND
7 PCIEXT0
8 PCIEXC0
9 VDD
10 SMBDAT
11 SMBCLK
12 VDD
13 PCIEXC1
14 PCIEXT1
15 GND
16 VDD
17 vCLKREQ1#
18 IREF
19 GNDA
20 VDDA
PIN TYPE
DESCRIPTION
3.3V input for selecting PLL Band Width
IN
0 = low, 1= high
IN True Input for differential reference clock.
IN Complementary Input for differential reference clock.
Output enable for PCI Expres s output pair 0.
IN
0 = enabled, 1 =disabled
PWR
Power supply, nominal 3.3V
PWR
Ground pin.
OU T
True clock of differential PCI_Express pair.
OU T
Complementary clock of differential PCI_Express pair.
PWR
Power supply, nominal 3.3V
I/O Data pin of SMBUS circuitry, 5V tolerant
IN Clock pin of SMBUS circuitry, 5V tolerant
PWR
Power supply, nominal 3.3V
OU T
Complementary clock of differential PCI_Express pair.
OU T
True clock of differential PCI_Express pair.
PWR
Ground pin.
PWR
Power supply, nominal 3.3V
Output enable for PCI Expres s output pair 1.
IN
0 = enabled, 1 =disabled
This pin establishes the reference for the differential current-mode
OU T
output pairs. It requires a fixed precision resistor to ground. 475ohm is
the standard value for 100ohm differential impedance. Other
PWR
impedances require different values. See data sheet.
Ground pin for the PLL c ore.
PWR
3.3V power for the PLL core.
Note:
Pins preceeded by ' v ' have internal 120K ohm pull down resistors
IDT® Two Output Differential Buffer for PCIe Gen1 & Gen2
2
852 REV Q 08/27/13


Features Two Output Differential Buffer for PCIe Gen1 & Gen2 DATASHEET ICS9DB102 Descr iption The ICS9DB102 zero-delay buffer supports PCI Express clocking requireme nts. The ICS9DB102 is driven by a diffe rential SRC output pair from an ICS CK4 10/CK505-compliant main clock. It atten uates jitter on the input clock and has a selectable PLL Band Width to maximiz e performance in systems with or withou t Spread-Spectrum clocking. Output Feat ures • 2 - 0.7V current mode differen tial output pairs (HCSL) Features/Bene fits • CLKREQ# pin for outputs 1 and 4/output enable for Express Card applic ations • PLL or bypass mode/PLL can d ejitter incoming clock • Selectable P LL bandwidth/minimizes jitter peaking i n downstream PLL’s • Spread Spectru m Compatible/tracks spreading input clo ck for low EMI • SMBus Interface/unus ed outputs can be disabled • Industri al temperature range available Key Spec ifications • Cycle-to-cycle jitter < 35ps • Output-to-output skew < 25ps Functional Block Diagram CLKREQ0# CLKREQ1# C.
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