ICS9DB104 Buffer Datasheet

ICS9DB104 Datasheet, PDF, Equivalent


Part Number

ICS9DB104

Description

Four Output Differential Buffer

Manufacture

Renesas

Total Page 15 Pages
Datasheet
Download ICS9DB104 Datasheet


ICS9DB104
Integrated
Circuit
Systems, Inc.
ICS9DB104
(Not recommended for new designs)
Four Output Differential Buffer for PCI-Express
Recommended Application:
Pin Configuration
DB400 Intel Yellow Cover part with PCI-Express support.
VDD 1
28 VDDA
Output Features:
• 4 - 0.7V current-mode differential output pairs
• Supports zero delay buffer mode and fanout mode
• Bandwidth programming available
SRC_IN 2
SRC_IN# 3
GND 4
VDD 5
DIF_1 6
27 GNDA
26 IREF
25 GND
24 VDD
23 DIF_6
Key Specifications:
• Outputs cycle-cycle jitter: < 50ps
• Outputs skew: < 50ps
r• +/- 300ppm frequency accuracy on output clocks
foFeatures/Benefits:
• Supports tight ppm accuracy clocks for Serial-ATA
d• Spread spectrum modulation tolerant, 0 to -0.5% down
spread and +/- 0.25% center spread
e• Supports undriven differential output pair in PD# and
Not recnoemwmdeensdignsSRC_STOP# for power management.
DIF_1# 7
OE_1 8
DIF_2 9
DIF_2# 10
VDD 11
BYPASS#/PLL 12
SCLK 13
SDATA 14
22 DIF_6#
21 OE_6
20 DIF_5
19 DIF_5#
18 VDD
17 HIGH_BW#
16 SRC_STOP#
15 PD#
28-pin SSOP & TSSOP
0767E—12/14/07

ICS9DB104
Integrated
Circuit
Systems, Inc.
ICS9DB104
(Not recommended for new designs)
Pin Description
PIN # PIN NAME
1 VDD
2 SRC_IN
3 SRC_IN#
4 GND
5 VDD
6 DIF_1
7 DIF_1#
8 OE_1
9 DIF_2
10 DIF_2#
11 VDD
12 BYPASS#/PLL
13 SCLK
14 SDATA
15 PD#
16 SRC_STOP#
17 HIGH_BW#
18 VDD
19 DIF_5#
20 DIF_5
21 OE_6
22 DIF_6#
23 DIF_6
24 VDD
25 GND
26 IREF
27 GNDA
28 VDDA
PIN TYPE
DESCRIPTION
PWR
IN
IN
PWR
PWR
OUT
OUT
IN
OUT
OUT
PWR
IN
IN
I/O
Power supply, nominal 3.3V
0.7 V Differential SRC TRUE input
0.7 V Differential SRC COMPLEMENTARY input
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock outputs
0.7V differential complement clock outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock outputs
0.7V differential complement clock outputs
Power supply, nominal 3.3V
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
IN
Asynchronous active low input pin used to power down the device. The
internal clocks are disabled and the VCO and the crystal are stopped.
IN
IN
PWR
OUT
OUT
IN
OUT
OUT
PWR
PWR
OUT
PWR
PWR
Active low input to stop diff outputs.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
Power supply, nominal 3.3V
0.7V differential complement clock outputs
0.7V differential true clock outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
0.7V differential complement clock outputs
0.7V differential true clock outputs
Power supply, nominal 3.3V
Ground pin.
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
0767E—12/14/07
2


Features Integrated Circuit Systems, Inc. ICS9DB 104 (Not recommended for new designs) Four Output Differential Buffer for PCI -Express Recommended Application: Pin Configuration DB400 Intel Yellow Cove r part with PCI-Express support. VDD 1 28 VDDA Output Features: • 4 - 0.7 V current-mode differential output pair s • Supports zero delay buffer mode a nd fanout mode • Bandwidth programmin g available SRC_IN 2 SRC_IN# 3 GND 4 V DD 5 DIF_1 6 27 GNDA 26 IREF 25 GND 24 VDD 23 DIF_6 ICS9DB104 Key Specifica tions: • Outputs cycle-cycle jitter: < 50ps • Outputs skew: < 50ps r• +/ - 300ppm frequency accuracy on output c locks foFeatures/Benefits: • Supports tight ppm accuracy clocks for Serial-A TA d• Spread spectrum modulation tole rant, 0 to -0.5% down spread and +/- 0. 25% center spread e• Supports undrive n differential output pair in PD# and N ot recnoemwmdeensdignsSRC_STOP# for pow er management. DIF_1# 7 OE_1 8 DIF_2 9 DIF_2# 10 VDD 11 BYPASS#/PLL 12 SCLK 13 SDATA 14 22 DIF_6# 21 OE_6 20 DIF_5 19 .
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