9DB306 Attenuator Datasheet

9DB306 Datasheet, PDF, Equivalent


Part Number

9DB306

Description

PCI Express Jitter Attenuator

Manufacture

Renesas

Total Page 18 Pages
Datasheet
Download 9DB306 Datasheet


9DB306
PCI Express Jitter Attenuator
9DB306
Data Sheet
GENERAL DESCRIPTION
The 9DB306 is a high performance 1-to-6 Differential-to-
LVPECL Jitter Attenuator designed for use in PCI Express™
systems. In some PCI Express systems, such as those found
in desktop PCs, the PCI Express clocks are generated from a
low bandwidth, high phase noise PLL frequency synthesizer. In
these systems, a zero delay buffer may be required to attenuate
high frequency random and deterministic jitter components from
the PLL synthesizer and from the system board. The 9DB306
has 2 PLL bandwidth modes. In low bandwidth mode, the PLL
loop BW is about 500kHz and this setting will attenuate much of
the jitter from the reference clock input while being high enough
to pass a triangular input spread spectrum profile. There is also
a high bandwidth mode which sets the PLL bandwidth at 1MHz
which will pass more spread spectrum modulation.
For serdes which have x30 reference multipliers instead of x25
multipliers, 5 of the 6 PCI Express outputs (PCIEX1:5) can be
set for 125MHz instead of 100MHz by configuring the appropriate
frequency select pins (FS0:1). Output PCIEX0 will always run at
the reference clock frequency (usually 100MHz) in desktop PC PCI
Express Applications.
FEATURES
Six differential LVPECL output pairs
One differential clock input
CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
Maximum output frequency: 140MHz
Input frequency range: 90MHz - 140MHz
VCO range: 450MHz - 700MHz
Output skew: 135ps (maximum)
Cycle-to-Cycle jitter: 30ps (maximum)
RMS phase jitter @ 100MHz, (1.5MHz - 22MHz): 3ps (typical)
3.3V operating supply
0°C to 70°C ambient operating temperature
Available in lead-free (RoHS 6) package
Industrial temperature information available upon request
BLOCK DIAGRAM
nOE0
1 Disabled
0 Enabled
CLK
nCLK
Buffer
Phase
Detector
Loop
Filter
VCO
÷5
Internal Feedback
BYPASS
nOE1
1 Disabled
0 Enabled
0
÷5
1
0 ÷4
1 ÷5
FS0
0
1
0 ÷5 0
1 ÷4
1
FS1
PCIEXT0
nPCIEXC0
PCIEXT1
nPCIEXC1
PCIEXT2
nPCIEXC2
PCIEXT3
nPCIEXC3
PCIEXT4
nPCIEXC4
PCIEXT5
nPCIEXC5
PIN ASSIGNMENT
VEE
PCIEXT1
PCIEXC1
PCIEXT2
PCIEXC2
VCC
nOE0
nOE1
VCC
PCIEXC3
PCIEXT3
PCIEXC4
PCIEXT4
VEE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VCC
27 PCIEXC0
26 PCIEXT0
25 FS0
24 nCLK
23 CLK
22 PLL_BW
21 VCCA
20 VEE
19 BYPASS
18 FS1
17 PCIEXT5
16 PCIEXC5
15 VCC
9DB306
28-Lead TSSOP, 173-MIL
4.4mm x 9.7mm x 0.925mm
body package
L Package
Top View
9DB306
28-Lead, 209-MIL SSOP
5.3mm x 10.2mm x 1.75mm
body package
F Package
Top View
©2016 Integrated Device Technology, Inc
1
Revision C February 18, 2016

9DB306
9DB306 Data Sheet
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 14, 20
2, 3
4, 5
6, 9, 15, 28
7, 8
10, 11
12, 13
16, 17
18
19
V
EE
PCIEXT1,
PCIEXC1
PCIEXT2,
PCIEXC2
V
CC
nOE0, nOE1
PCIEXC3,
PCIEXT3
PCIEXC4,
PCIEXT4
PCIEXC5,
PCIEXT5
FS1
BYPASS
Power
Output
Output
Power
Input
Output
Output
Output
Input
Negative supply pins.
Differential output pairs. LVPECL interface levels.
Differential output pairs. LVPECL interface levels.
Core supply pins.
Output enable. When HIGH, forces true outputs (PCIEXTx) to go LOW
Pulldown and the inverted outputs (PCIEXCx) to go HIGH. When LOW, outputs
are enabled. LVCMOS/LVTTL interface levels.
Differential output pairs. LVPECL interface levels.
Differential output pairs. LVPECL interface levels.
Differential output pairs. LVPECL interface levels.
Pulldown Frequency select pin. LVCMOS/LVTTL interface levels.
Pulldown
Bypass select pin. When HIGH, the PLL is in bypass mode, and the
device can function as a 1:6 buffer. LVCMOS/LVTTL interface levels.
21 V Power
CCA
Analog supply pin. Requires 24Ω series resistor.
22
PLL_BW
Input Pullup Selects PLL Bandwidth input. LVCMOS/LVTTL interface levels.
23 CLK Input Pulldown Non-inverting differential clock input.
24
nCLK
Input
Pullup/
Pulldown
Inverting differential clock input. V /2 default when left floating.
CC
25 FS0 Input Pullup Frequency select pin. LVCMOS/LVTTL interface levels.
26, 27
PCIEXT0,
PCIEXC0
Output
Differential output pairs. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
C
IN
R
PULLUP
R
PULLDOWN
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
TABLE 3A. RATIO OF OUTPUT FREQUENCY TO
INPUT FREQUENCY FUNCTION TABLE, FS0
Inputs
Outputs
FS0 PCIEX0 PCIEX1 PCIEX2
0 1 5/4 5/4
1111
TABLE 3B. RATIO OF OUTPUT FREQUENCY TO
INPUT FREQUENCY FUNCTION TABLE, FS1
Inputs
Outputs
FS1 PCIEX3 PCIEX4 PCIEX5
0111
1 5/4 5/4 5/4
TABLE 3C. OUTPUT ENABLE
FUNCTION TABLE, nOE0
Inputs Outputs
nOE0 PCIEX0:2
0 Enabled
1 Disabled
TABLE 3D. OUTPUT ENABLE
FUNCTION TABLE, nOE1
Inputs Outputs
nOE1 PCIEX3:5
0 Enabled
1 Disabled
TABLE 3E. PLL BANDWIDTH
FUNCTION TABLE
Inputs
Bandwidth
PLL_BW
0 500kHz
1 1MHz
TABLE 3F. PLL MODE
FUNCTION TABLE
Inputs
PLL Mode
BYPASS
1 Disabled
0 Enabled
©2016 Integrated Device Technology, Inc
2
Revision C February 18, 2016


Features PCI Express Jitter Attenuator 9DB306 Da ta Sheet GENERAL DESCRIPTION The 9DB30 6 is a high performance 1-to-6 Differen tial-toLVPECL Jitter Attenuator designe d for use in PCI Express™ systems. In some PCI Express systems, such as thos e found in desktop PCs, the PCI Express clocks are generated from a low bandwi dth, high phase noise PLL frequency syn thesizer. In these systems, a zero dela y buffer may be required to attenuate h igh frequency random and deterministic jitter components from the PLL synthesi zer and from the system board. The 9DB3 06 has 2 PLL bandwidth modes. In low ba ndwidth mode, the PLL loop BW is about 500kHz and this setting will attenuate much of the jitter from the reference c lock input while being high enough to p ass a triangular input spread spectrum profile. There is also a high bandwidt h mode which sets the PLL bandwidth at 1MHz which will pass more spread spectr um modulation. For serdes which have x3 0 reference multipliers instead of x25 multipliers, 5 of the 6 PCI .
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