9DB401C Buffer Datasheet

9DB401C Datasheet, PDF, Equivalent


Part Number

9DB401C

Description

Four Output Differential Buffer

Manufacture

Renesas

Total Page 18 Pages
Datasheet
Download 9DB401C Datasheet


9DB401C
Four Output Differential Buffer for PCI Express
DATASHEET
9DB401C
Description
The 9DB401C is a DB400 Version 2.0 Yellow Cover part with
PCI Express support. It can be used in PC or embedded
systems to provide outputs that have low cycle-to-cycle jitter
(50ps), low output-to-output skew (100ps), and are PCI Express
gen 1 compliant. The 9DB401C supports a 1 to 4 output
configuration, taking a spread or non spread differential HCSL
input from a CK410(B) main clock such as 954101 and
932S401, or any other differential HCSL pair. 9DB401C can
generate HCSL or LVDS outputs from 50 to 200MHz in PLL
mode or 0 to 400Mhz in bypass mode. There are two de-jittering
modes available selectable through the HIGH_BW# input pin,
high bandwidth mode provides de-jittering for spread inputs and
low bandwidth mode provides extra de-jittering for non-spread
inputs. The SRC_STOP#, PD#, and OE real-time input pins
provide completely programmable power management control.
Output Features
• 4 - 0.7V HCSL or LVDS differential output pairs
• Supports zero delay buffer mode and fanout mode
• Bandwidth programming available
Features/Benefits
• Spread spectrum modulation tolerant, 0 to -0.5% down
spread and +/- 0.25% center spread
• Supports undriven differential outputs in PD# and
SRC_STOP# modes for power management.
Key Specifications
• Outputs cycle-cycle jitter: < 50ps
• Outputs skew: < 50ps
• Extended frequency range in bypass mode:
Revision B: up to 333.33MHz
Revision C: up to 400MHz
• Real-time PLL lock detect output pin
• 28-pin SSOP/TSSOP package
• Available in RoHS compliant packaging
Functional Block Diagram
OE (1,6) 2
-SRC_IN
-SRC_IN#
Spread
Compatible
PLL
-PD
-BYPASS#/PLL
-SDATA
-SCLK
Control
Logic
M
U
X
Stop
Logic
4
DIF (1,2,5,6)
IREF
Note: Polarities shown for OE_INV = 0.
IDT® Four Output Differential Buffer for PCI Express
1
9DB401C REV H 01/27/11

9DB401C
9DB401C
Four Output Differential Buffer for PCI Express
Pin Configuration
VDD 1
SRC_IN 2
SRC_IN# 3
GND 4
VDD 5
DIF_1 6
DIF_1# 7
OE_1 8
DIF_2 9
DIF_2# 10
VDD 11
BYPASS#/PLL 12
SCLK 13
SDATA 14
OE_INV = 0
28 VDDA
27 GNDA
26 IREF
25 OE_INV
24 VDD
23 DIF_6
22 DIF_6#
21 OE_6
20 DIF_5
19 DIF_5#
18 VDD
17 HIGH_BW#
16 SRC_STOP#
15 PD#
VDD 1
SRC_IN 2
SRC_IN# 3
GND 4
VDD 5
DIF_1 6
DIF_1# 7
OE1# 8
DIF_2 9
DIF_2# 10
VDD 11
BYPASS#/PLL 12
SCLK 13
SDATA 14
OE_INV = 1
28 VDDA
27 GNDA
26 IREF
25 OE_INV
24 VDD
23 DIF_6
22 DIF_6#
21 OE6#
20 DIF_5
19 DIF_5#
18 VDD
17 HIGH_BW#
16 SRC_STOP
15 PD
28-pin SSOP & TSSOP
Polarity Inversion Pin List Table
O E_INV
Pins 0
1
8 OE_1
O E1#
15 PD#
PD
16
D IF _ST O P#
DIF _ST O P
21 OE_6
O E6#
Power Groups
Pin Number
VDD
GND
14
5,11,18, 24
4
N/A 27
28 27
Description
SRC_IN/SRC_IN#
DIF(1,2,5,6)
IREF
Analog VDD & GND for PLL core
IDT® Four Output Differential Buffer for PCI Express
2
9DB401C REV H 01/27/11


Features Four Output Differential Buffer for PCI Express DATASHEET 9DB401C Description The 9DB401C is a DB400 Version 2.0 Yel low Cover part with PCI Express support . It can be used in PC or embedded syst ems to provide outputs that have low cy cle-to-cycle jitter (50ps), low output- to-output skew (100ps), and are PCI Exp ress gen 1 compliant. The 9DB401C suppo rts a 1 to 4 output configuration, taki ng a spread or non spread differential HCSL input from a CK410(B) main clock s uch as 954101 and 932S401, or any other differential HCSL pair. 9DB401C can ge nerate HCSL or LVDS outputs from 50 to 200MHz in PLL mode or 0 to 400Mhz in by pass mode. There are two de-jittering m odes available selectable through the H IGH_BW# input pin, high bandwidth mode provides de-jittering for spread inputs and low bandwidth mode provides extra de-jittering for non-spread inputs. The SRC_STOP#, PD#, and OE real-time input pins provide completely programmable p ower management control. Output Features • 4 - 0.7V HCSL or LVD.
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