ICS9DB403D Buffer Datasheet

ICS9DB403D Datasheet, PDF, Equivalent


Part Number

ICS9DB403D

Description

Four Output Differential Buffer

Manufacture

Renesas

Total Page 20 Pages
Datasheet
Download ICS9DB403D Datasheet


ICS9DB403D
Four Output Differential Buffer for PCIe Gen 1 and Gen 2
DATASHEET
ICS9DB403D
Description
Features/Benefits
The ICS9DB403 is compatible with the Intel DB400v2 Differential
Buffer Specification.This buffer provides 4 PCI-Express Gen2 clocks.
The ICS9DB403 is driven by a differential output pair from a
CK410B+, CK505 or CK509B main clock generator.
Spread spectrum modulation tolerant, 0 to -0.5% down
spread and +/- 0.25% center spread.
Supports undriven differential outputs in PD# and
SRC_STOP# modes for power management.
Output Features
• 4 - 0.7V current-mode differential output pairs
• Supports zero delay buffer mode and fanout mode
• Bandwidth programming available
• 50-100 MHz operation in PLL mode
• 50-400 MHz operation in Bypass mode
Key Specifications
• Outputs cycle-cycle jitter < 50ps
• Outputs skew: 50ps
• Phase jitter: PCIe Gen1 < 86ps peak to peak
• Phase jitter: PCIe Gen2 < 3.0/3.1ps rms
• 28-pin SSOP/TSSOP pacakge
• Available in RoHS compliant packaging
• Supports Commercial (0 to +70°C) and Industrial (-40 to
+85°C) temperature ranges
Functional Block Diagram
24
OE-(O6,5E,(26,1, )1)
SRC_IN
SRC_IN#
SPREAD
COMPATIBLE
PLL
4
M
STOP
U LOGIC
X
PD
BYPASS#/PLL
SDATA
SCLK
CONTROL
LOGIC
DIF(6,5,2,1)
IREF
Note: Polarities shown for OE_INV = 0.
IDT® Four Output Differential Buffer for PCIe and Gen 1 and Gen 2
1
ICS9DB403D REV R 11/1/12

ICS9DB403D
ICS9DB403D
Four Output Differential Buffer for PCIe for Gen 1 and Gen 2
Pin Configuration
VDDR 1
28 VDDA
SRC_IN 2
27 GNDA
SRC_IN# 3
26 IREF
GND 4
25 OE_INV
VDD 5
24 VDD
DIF_1 6
23 DIF_6
DIF_1# 7
22 DIF_6#
OE_1 8
21 OE_6
DIF_2 9
20 DIF_5
DIF_2# 10
19 DIF_5#
VDD 11
18 VDD
BYPASS#/PLL 12
17 HIGH_BW#
SCLK 13
16 DIF_STOP#
SDATA 14
15 PD#
OE_INV = 0
VDDR 1
28 VDDA
SRC_IN 2
27 GNDA
SRC_IN# 3
26 IREF
GND 4
25 OE_INV
VDD 5
24 VDD
DIF_1 6
23 DIF_6
DIF_1# 7
22 DIF_6#
OE1# 8
21 OE6#
DIF_2 9
20 DIF_5
DIF_2# 10
19 DIF_5#
VDD 11
18 VDD
BYPASS#/PLL 12
17 HIGH_BW#
SCLK 13
16 DIF_STOP
SDATA 14
15 PD
OE_INV = 1
28-pin SSOP & TSSOP
Polarity Inversion Pin List Table
O E_INV
Pins 0
1
8 OE_1
O E1#
15 PD#
PD
16
D IF _ST O P#
DIF _ST O P
21 OE_6
O E6#
Power Groups
Pin Number
VDD
GND
14
5,11,18, 24
4
N/A 27
28 27
Description
SRC_IN/SRC_IN#
DIF(1,2,5,6)
IREF
Analog VDD & GND for PLL core
IDT® Four Output Differential Buffer for PCIe Gen 1 and Gen 2
2
ICS9DB403D REV R 11/1/12


Features Four Output Differential Buffer for PCIe Gen 1 and Gen 2 DATASHEET ICS9DB403D Description Features/Benefits The IC S9DB403 is compatible with the Intel DB 400v2 Differential Buffer Specification .This buffer provides 4 PCI-Express Gen 2 clocks. The ICS9DB403 is driven by a differential output pair from a CK410B+ , CK505 or CK509B main clock generator. • • Spread spectrum modulation t olerant, 0 to -0.5% down spread and +/- 0.25% center spread. Supports undriven differential outputs in PD# and SRC_ST OP# modes for power management. Output Features • 4 - 0.7V current-mode dif ferential output pairs • Supports zer o delay buffer mode and fanout mode • Bandwidth programming available • 50 -100 MHz operation in PLL mode • 50-4 00 MHz operation in Bypass mode Key Sp ecifications • Outputs cycle-cycle ji tter < 50ps • Outputs skew: 50ps • Phase jitter: PCIe Gen1 < 86ps peak to peak • Phase jitter: PCIe Gen2 < 3.0/ 3.1ps rms • 28-pin SSOP/TSSOP pacakge • Available in RoHS compliant packaging • Suppo.
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