ICS9DBL411A Buffer Datasheet

ICS9DBL411A Datasheet, PDF, Equivalent


Part Number

ICS9DBL411A

Description

Four Output Differential Fanout Buffer

Manufacture

Renesas

Total Page 10 Pages
Datasheet
Download ICS9DBL411A Datasheet


ICS9DBL411A
DATASHEET
Four Output Differential Fanout Buffer for
PCI Express Gen 1 & 2
ICS9DBL411A
Recommended Application:
PCI-Express fanout buffer
Output Features:
• 4 - low power differential output pairs
• Individual OE# control of each output pair
Key Specifications:
• Output cycle-cycle jitter < 25ps additive
• Output to output skew: < 50ps
Features/Benefits:
• Low power differential fanout buffer for PCI-
Express and CPU clocks
• 20-pin MLF or TSSOP packaging
General Description:
The ICS9DBL411 is a 4 output lower power
differential buffer. Each output has its own OE#
pin. It has a maximum input frequency of 400 MHz.
Power Groups
Pin Number (TSSOP)
VDD
GND
9,18 10,17
45
Pin Number (MLF)
VDD
GND
6,15 7,14
12
Description
VDD_IO for DIF(3:0)
3.3V Analog VDD & GND
Description
VDD_IO for DIF(3:0)
3.3V Analog VDD & GND
Funtional Block Diagram
OE#(3:0)
4
DIF_INT
DIF_INC
STOP
LOGIC
4
DIF_LPR(3:0)
IDT® Four Output Differential Buffer for PCI Express
1
1250C—06/28/12

ICS9DBL411A
ICS9DBL411A
Four Output Differential Buffer for PCI Express
Advance Information
Pin Configuration
OE0# 1
DIF_INC 2
DIF_INT 3
VDDA 4
GNDA 5
OE3# 6
DIF3C_LPR 7
DIF3T_LPR 8
VDD_IO 9
GND 10
20 DIF0T_LPR
19 DIF0C_LPR
18 VDD_IO
17 GND
16 OE1#
15 DIF1T_LPR
14 DIF1C_LPR
13 OE2#
12 DIF2T_LPR
11 DIF2C_LPR
20-pin TSSOP
20 19 18 17 16
VDDA 1
15 VDD_IO
GNDA 2
14 GND
OE3# 3 9DBL411 13 OE1#
DIF3C_LPR 4
12 DIF1T_LPR
DIF3T_LPR 5
11 DIF1C_LPR
6 7 8 9 10
IDT® Four Output Differential Buffer for PCI Express
20-pin MLF
2
1250C—06/28/12


Features DATASHEET Four Output Differential Fano ut Buffer for PCI Express Gen 1 & 2 IC S9DBL411A Recommended Application: PCI -Express fanout buffer Output Features: • 4 - low power differential output pairs • Individual OE# control of eac h output pair Key Specifications: • O utput cycle-cycle jitter < 25ps additiv e • Output to output skew: < 50ps Fe atures/Benefits: • Low power differen tial fanout buffer for PCIExpress and C PU clocks • 20-pin MLF or TSSOP packa ging General Description: The ICS9DBL41 1 is a 4 output lower power differentia l buffer. Each output has its own OE# p in. It has a maximum input frequency of 400 MHz. Power Groups Pin Number (TS SOP) VDD GND 9,18 10,17 45 Pin Num ber (MLF) VDD GND 6,15 7,14 12 Des cription VDD_IO for DIF(3:0) 3.3V Analo g VDD & GND Description VDD_IO for DIF( 3:0) 3.3V Analog VDD & GND Funtional B lock Diagram OE#(3:0) 4 DIF_INT DIF_ INC STOP LOGIC 4 DIF_LPR(3:0) IDT® Four Output Differential Buffer for PCI Express 1 1250C—06/28/12 ICS9DBL.
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