CD54HCT154 Decoder/Demultiplexer Datasheet

CD54HCT154 Datasheet, PDF, Equivalent


Part Number

CD54HCT154

Description

4- to 16-Line Decoder/Demultiplexer

Manufacture

etcTI

Total Page 15 Pages
Datasheet
Download CD54HCT154 Datasheet


CD54HCT154
Data sheet acquired from Harris Semiconductor
SCHS152D
September 1997 - Revised June 2004
CD54HC154, CD74HC154,
CD54HCT154, CD74HCT154
High-Speed CMOS Logic
4- to 16-Line Decoder/Demultiplexer
[ /Title
(CD74
HC154
,
CD74
HCT15
4)
/Sub-
ject
(High
Speed
CMOS
Logic
4-to-16
Line
Decod
er/Dem
Features
• Two Enable Inputs to Facilitate Demultiplexing and
Cascading Functions
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30%of VCC at
VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
VIL= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
Description
A High on either enable input forces the output into the High
state. The demultiplexing function is performed by using the
four input lines, A0 to A3, to select the output lines Y0 to
Y15, and using one enable as the data input while holding
the other enable low.
Ordering Information
PART NUMBER
CD54HC154F3A
CD54HCT154F3A
CD74HC154E
CD74HC154EN
CD74HC154M
CD74HC154M96
CD74HCT154E
CD74HCT154EN
CD74HCT154M
CD74HCT154M96
TEMP. RANGE
(oC)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
24 Ld CERDIP
24 Ld CERDIP
24 Ld PDIP
24 Ld PDIP
24 Ld SOIC
24 Ld SOIC
24 Ld PDIP
24 Ld PDIP
24 Ld SOIC
24 Ld SOIC
The ’HC154 and ’HCT154 are 4- to 16-line NOTE: When ordering, use the entire part number. The suffix 96
decoders/demultiplexers with two enable inputs, E1 and E2. denotes tape and reel.
Pinout
CD54HC154, CD54HCT154
(CERDIP)
CD74HC154, CD74HCT154
(PDIP, SOIC)
TOP VIEW
Y0 1
Y1 2
Y2 3
Y3 4
Y4 5
Y5 6
Y6 7
Y7 8
Y8 9
Y9 10
Y10 11
GND 12
24 VCC
23 A0
22 A1
21 A2
20 A3
19 E2
18 E1
17 Y15
16 Y14
15 Y13
14 Y12
13 Y11
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2004, Texas Instruments Incorporated
1

CD54HCT154
CD54HC154, CD74HC154, CD54HCT154, CD74HCT154
Functional Diagram
A0 23
A1 22
A2 21
20
A3
E1 18
E2 19
1
Y0
2
Y1
3
Y2
4
Y3
5
Y4
6
Y5
7
Y6
8
Y7
9
Y8
10
Y9
11
Y10
13
Y11
14
Y12
15
Y13
16
Y14
17
Y15
GND = 12
VCC = 24
TRUTH TABLE
INPUTS
OUTPUTS
E1 E2 A3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15
L L L L L L LHHHHHHHHHHHHHHH
L L L L LHHLHHHHHHHHHHHHHH
L L L LHLHHLHHHHHHHHHHHHH
L L L LHHHHHLHHHHHHHHHHHH
L L LHL LHHHHLHHHHHHHHHHH
L L LHLHHHHHHLHHHHHHHHHH
L L LHHLHHHHHHLHHHHHHHHH
L L LHHHHHHHHHHLHHHHHHHH
L LHL L LHHHHHHHHLHHHHHHH
L LHL LHHHHHHHHHHLHHHHHH
L LHLHLHHHHHHHHHHLHHHHH
L LHLHHHHHHHHHHHHHLHHHH
L LHHL LHHHHHHHHHHHHLHHH
L LHHLHHHHHHHHHHHHHHLHH
L LHHHLHHHHHHHHHHHHHHLH
L LHHHHHHHHHHHHHHHHHHHL
L HX X X XHHHHHHHHHHHHHHHH
HL XXXXHHHHHHHHHHHHHHHH
HHXXXXHHHHHHHHHHHHHHHH
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care
2


Features Data sheet acquired from Harris Semicond uctor SCHS152D September 1997 - Revised June 2004 CD54HC154, CD74HC154, CD54H CT154, CD74HCT154 High-Speed CMOS Logic 4- to 16-Line Decoder/Demultiplexer [ /Title (CD74 HC154 , CD74 HCT15 4) /Su bject (High Speed CMOS Logic 4-to-16 Li ne Decod er/Dem Features • Two Enabl e Inputs to Facilitate Demultiplexing a nd Cascading Functions • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wide O perating Temperature Range . . . -55oC to 125oC • Balanced Propagation Delay and Transition Times • Significant Power Reduction Compared to LSTTL Logic ICs • HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30%of VCC at VCC = 5V • HCT Types - 4.5V to 5.5V Operation - Direct LSTTL I nput Logic Compatibility, VIL= 0.8V (Ma x), VIH = 2V (Min) - CMOS Input Compati bility, Il ≤ 1µA at VOL, VOH Description A High on either enable input forces .
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