CD74HCT139

Data sheet acquired from Harris Semiconductor SCHS148D September 1997 - Revised October 2003 CD54HC139, CD74HC139, CD54HCT139, CD74HCT139 High-Speed CMOS Logic Dual 2- to 4-Line Decoder/Demultiplexer [ /Title (CD74 HC139 , CD74 HCT13 9) /Subject (High Speed CMOS Logic Dual 2-to-4 Line Decod Features Multifunction Capability - Binary to 1 of 4 Decoders or 1 to 4 Line Demultiplexer Active Low Mutually Exclusive Outputs Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads Wide Operating Temperature Range . . . -55oC to 125oC Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types - 2V to 6V Operation - High Noise Immunity: NIL = 30%, NIH = 30%of VCC at VCC = 5V HCT Types - 4.5V to 5.5V Operation - Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH Memory Decoding, Data Routing, Code Conversion Description The ’HC139 and ’HCT139 devices contain two independent binary to one of four decoders each with a single active low enable input (1E or 2E). Data on the select inputs (1A0 and 1A1 or 2A0 and 2A1) cause one of the four normally high outputs to go low. If the enable input is high all four outputs remain high. For demultiplexer operation the enable input is the data input. The enable input also functions as a chip select when these ...