5P49V5907 Generator Datasheet

5P49V5907 Datasheet, PDF, Equivalent


Part Number

5P49V5907

Description

Programmable Clock Generator

Manufacture

Renesas

Total Page 30 Pages
Datasheet
Download 5P49V5907 Datasheet


5P49V5907
Programmable Clock Generator
5P49V5907
DATASHEET
Description
The 5P49V5907 is a programmable clock generator intended
for high performance consumer, networking, industrial,
computing, and data-communications applications.
Configurations may be stored in on-chip One-Time
Programmable (OTP) memory or changed using I2C
interface. This is IDTs fifth generation of programmable clock
technology (VersaClock® 5).
The frequencies are generated from a single reference clock
or crystal. Two select pins allow up to 4 different
configurations to be programmed and accessible using
processor GPIOs or bootstrapping. The different selections
may be used for different operating modes (full function,
partial function, partial power-down), regional standards (US,
Japan, Europe) or system production margin testing.
The device may be configured to use one of two I2C
addresses to allow multiple devices to be used in a system.
Pin Assignment
NC
XOUT
XIN/REF
VDDA
VDDO
OUT7
OUT7B
OUT6
OUT6B
SD/OE
40 39 38 37 36 35 34 33 32 31
1 30
2 29
3 28
4 27
5 26
EPAD
6 25
7 24
8 23
9 22
10 21
11 12 13 14 15 16 17 18 19 20
VDDO2
OUT2
OUT2B
VDD
VDD
VDD_CORE
OUT3
OUT3B
NC
NC
40-pin VFQFPN
Features
Generates up to four independent output frequencies with a
total of 7 differential outputs and one reference output
Supports multiple differential output I/O standards:
– Three universal outputs pairs with each configurable
as one differential output pair (LVDS, LVPECL or
regular HCSL) or two LVCMOS outputs. Frequency of
each output pair can be individually programmed
– Four copies of Low Power HCSL(LP-HCSL) outputs.
Programmable frequency:
– See Output Features and Descriptions for details
One reference LVCMOS output clock
High performance, low phase noise PLL, <0.7 ps RMS
typical phase jitter on outputs:
– PCIe Gen1, 2, 3 compliant clock capability
– USB 3.0 compliant clock capability
– 1 GbE and 10 GbE
Four fractional output dividers (FODs)
Independent Spread Spectrum capability from each
fractional output divider (FOD)
Four banks of internal non-volatile in-system
programmable or factory programmable OTP memory
I2C serial programming interface
Input frequency ranges:
– LVCMOS Reference Clock Input (XIN/REF) – 1MHz
to 200MHz
– Crystal frequency range: 8MHz to 40MHz
Output frequency ranges:
– LVCMOS Clock Outputs – 1MHz to 200MHz
– LP-HCSL Clock Outputs – 1MHz to 200MHz
– Other Differential Clock Outputs – 1MHz to 350MHz
Programmable loop bandwidth
Programmable crystal load capacitance
Power-down mode
Mixed voltage operation:
– 1.8V core
– 1.8V VDDO for 4 LP-HCSL outputs
– 1.8V to 3.3V VDDO for other outputs
(3 programmable differential outputs and 1 reference
output)
– See Pin Descriptions for details
Packaged in 40-pin 5mm x 5mm VFQFPN (NDG40)
-40° to +85°C industrial temperature operation
5P49V5907 MARCH 3, 2017
1 ©2017 Integrated Device Technology, Inc.

5P49V5907
5P49V5907 DATASHEET
Functional Block Diagram
XIN/REF
XOUT
SD/OE
SEL1/SDA
SEL0/SCL
VDDA
VDD_CORE
VDDO
OE_buffer
VDD
OTP
and
Control Logic
PLL
Applications
Ethernet switch/router
PCI Express 1.0/2.0/3.0
Broadcast video/audio timing
Multi-function printer
Processor and FPGA clocking
Any-frequency clock conversion
MSAN/DSLAM/PON
Fiber Channel, SAN
Telecom line cards
1 GbE and 10 GbE
FOD1
FOD2
FOD3
FOD4
PROGRAMMABLE CLOCK GENERATOR
2
VDDO0
OUT0_SEL_I2CB
VDDO1
OUT1
OUT1B
VDDO2
OUT2
OUT2B
OEB3,5
OUT3, 5
OEB6,7
OUT6, 7
VDDO4
OUT4
OUT4B
MARCH 3, 2017


Features Programmable Clock Generator 5P49V5907 DATASHEET Description The 5P49V5907 i s a programmable clock generator intend ed for high performance consumer, netwo rking, industrial, computing, and data- communications applications. Configurat ions may be stored in on-chip One-Time Programmable (OTP) memory or changed us ing I2C interface. This is IDTs fifth g eneration of programmable clock technol ogy (VersaClock® 5). The frequencies a re generated from a single reference cl ock or crystal. Two select pins allow u p to 4 different configurations to be p rogrammed and accessible using processo r GPIOs or bootstrapping. The different selections may be used for different o perating modes (full function, partial function, partial power-down), regional standards (US, Japan, Europe) or syste m production margin testing. The device may be configured to use one of two I2 C addresses to allow multiple devices t o be used in a system. Pin Assignment OUT0_SEL_I2CB VDDO0 OE_buffer VDD VDDO NC OEB6,7 VDDO1 OUT1 OUT1.
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