SN74HC00-Q1 GATE Datasheet

SN74HC00-Q1 Datasheet, PDF, Equivalent


Part Number

SN74HC00-Q1

Description

QUADRUPLE 2-INPUT POSITIVE-NAND GATE

Manufacture

etcTI

Total Page 13 Pages
Datasheet
Download SN74HC00-Q1 Datasheet


SN74HC00-Q1
D Qualified for Automotive Applications
D Wide Operating Voltage Range of 2 V to 6 V
D Outputs Can Drive Up To 10 LSTTL Loads
D Low Power Consumption, 40-µA Max ICC
D Typical tpd = 8 ns
D ±4-mA Output Drive at 5 V
D Low Input Current of 1 µA Max
SN74HC00-Q1
QUADRUPLE 2-INPUT POSITIVE-NAND GATE
SCLS575 − MARCH 2004 − REVISED APRIL 2008
D OR PW PACKAGE
(TOP VIEW)
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
14 VCC
13 4B
12 4A
11 4Y
10 3B
9 3A
8 3Y
description/ordering information
The SN74HC00 device contains four independent 2-input NAND gates. It performs the Boolean function
Y = A B or Y = A + B in positive logic.
ORDERING INFORMATION{
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 125°C
SOIC − D
TSSOP − PW
Reel of 2500
Reel of 2000
SN74HC00QDRQ1
SN74HC00QPWRQ1
HC00Q
HC00Q
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or see the TI web site at http://www.ti.com.
Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
FUNCTION TABLE
(each gate)
INPUTS
AB
OUTPUT
Y
HH
L
LX
H
XL
H
logic diagram (positive logic)
A
B
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2008, Texas Instruments Incorporated
1

SN74HC00-Q1
SN74HC00-Q1
QUADRUPLE 2-INPUT POSITIVE-NAND GATE
SCLS575 − MARCH 2004 − REVISED APRIL 2008
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN NOM MAX UNIT
VCC Supply voltage
2 5 6V
VCC = 2 V
1.5
VIH High-level input voltage
VCC = 4.5 V
3.15
V
VCC = 6 V
4.2
VCC = 2 V
0.5
VIL Low-level input voltage
VCC = 4.5 V
1.35 V
VCC = 6 V
1.8
VI Input voltage
0
VCC
V
VO Output voltage
0
VCC
V
VCC = 2 V
1000
t/v Input transition rise/fall time
VCC = 4.5 V
500 ns
VCC = 6 V
400
TA Operating free-air temperature
−40 125 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Features D Qualified for Automotive Applications D Wide Operating Voltage Range of 2 V t o 6 V D Outputs Can Drive Up To 10 LSTT L Loads D Low Power Consumption, 40-µA Max ICC D Typical tpd = 8 ns D ±4-mA Output Drive at 5 V D Low Input Current of 1 µA Max SN74HC00-Q1 QUADRUPLE 2- INPUT POSITIVE-NAND GATE SCLS575 − M ARCH 2004 − REVISED APRIL 2008 D OR P W PACKAGE (TOP VIEW) 1A 1B 1Y 2A 2B 2Y GND 1 2 3 4 5 6 7 14 VCC 13 4B 12 4A 11 4Y 10 3B 9 3A 8 3Y description/ord ering information The SN74HC00 device c ontains four independent 2-input NAND g ates. It performs the Boolean function Y = A • B or Y = A + B in positive lo gic. ORDERING INFORMATION{ TA PACKAG E‡ ORDERABLE PART NUMBER TOP-SIDE M ARKING −40°C to 125°C SOIC − D TSSOP − PW Reel of 2500 Reel of 2000 SN74HC00QDRQ1 SN74HC00QPWRQ1 HC00Q H C00Q † For the most current package and ordering information, see the Packa ge Option Addendum at the end of this document, or see the TI web site at http://www.ti.com. ‡ Package drawings, thermal d.
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