SN54HC20 GATES Datasheet

SN54HC20 Datasheet, PDF, Equivalent


Part Number

SN54HC20

Description

DUAL 4-INPUT POSITIVE-NAND GATES

Manufacture

etcTI

Total Page 22 Pages
Datasheet
Download SN54HC20 Datasheet


SN54HC20
D Wide Operating Voltage Range of 2 V to 6 V
D Outputs Can Drive Up To 10 LSTTL Loads
D Low Power Consumption, 20-µA Max ICC
SN54HC20 . . . J OR W PACKAGE
SN74HC20 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
1A
1B
NC
1C
1D
1Y
GND
1
2
3
4
5
6
7
14 VCC
13 2D
12 2C
11 NC
10 2B
9 2A
8 2Y
SN54HC20, SN74HC20
DUAL 4ĆINPUT POSITIVEĆNAND GATES
SCLS086F − DECEMBER 1982 − REVISED AUGUST 2003
D Typical tpd = 11 ns
D ±4-mA Output Drive at 5 V
D Low Input Current of 1 µA Max
SN54HC20 . . . FK PACKAGE
(TOP VIEW)
NC
3 2 1 20 19
4 18
2C
NC 5
17 NC
1C 6
16 NC
NC 7
15 NC
1D 8
14 2B
9 10 11 12 13
description/ordering information
NC − No internal connection
The ’HC20 devices contain two independent 4-input NAND gates. They perform the Boolean function
Y = A B C D or Y = A + B + C + D in positive logic.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP − N
Tube of 25
SN74HC20N
SN74HC20N
Tube of 50
SN74HC20D
SOIC − D
Reel of 2500
Reel of 250
SN74HC20DR
SN74HC20DT
HC20
−40°C to 85°C
SOP − NS
SSOP − DB
Reel of 2000
Reel of 2000
SN74HC20NSR
SN74HC20DBR
HC20
HC20
Tube of 90
SN74HC20PW
TSSOP − PW
Reel of 2000
Reel of 250
SN74HC20PWR
SN74HC20PWT
HC20
CDIP − J
Tube of 25
SNJ54HC20J
SNJ54HC20J
−55°C to 125°C CFP − W
Tube of 150
SNJ54HC20W
SNJ54HC20W
LCCC − FK
Tube of 55
SNJ54HC20FK
SNJ54HC20FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2003, Texas Instruments Incorporated
On products compliant to MILĆPRFĆ38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1

SN54HC20
SN54HC20, SN74HC20
DUAL 4ĆINPUT POSITIVEĆNAND GATES
SCLS086F − DECEMBER 1982 − REVISED AUGUST 2003
A
H
L
X
X
X
FUNCTION TABLE
(each gate)
INPUTS
BC
OUTPUT
DY
HHH
L
XXX
H
LXX
H
XLX
H
XXL
H
logic diagram (positive logic)
1A
1B
1C
1D
1
2
4
5
6 1Y
Pin numbers shown are for the D, DB, J, N, NS, PW, and W packages.
2A
2B
2C
2D
9
10
12
13
8 2Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Features D Wide Operating Voltage Range of 2 V to 6 V D Outputs Can Drive Up To 10 LSTTL Loads D Low Power Consumption, 20-µA Max ICC SN54HC20 . . . J OR W PACKAGE S N74HC20 . . . D, DB, N, NS, OR PW PACKA GE (TOP VIEW) 1A 1B NC 1C 1D 1Y GND 1 2 3 4 5 6 7 14 VCC 13 2D 12 2C 11 NC 10 2B 9 2A 8 2Y SN54HC20, SN74HC20 DUA L 4ĆINPUT POSITIVEĆNAND GATES SCLS086 F − DECEMBER 1982 − REVISED AUGUST 2003 D Typical tpd = 11 ns D ±4-mA Out put Drive at 5 V D Low Input Current of 1 µA Max SN54HC20 . . . FK PACKAGE (T OP VIEW) VCC NC 3 2 1 20 19 4 18 2C NC 5 17 NC 1C 6 16 NC NC 7 15 NC 1D 8 14 2B 9 10 11 12 13 2A 2D NC NC GND 1A 1Y 1B 2Y description/ord ering information NC − No internal c onnection The ’HC20 devices contain two independent 4-input NAND gates. The y perform the Boolean function Y = A B • C • D or Y = A + B + C + D in positive logic. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP − N Tube of 25 SN74HC20N SN74HC20N Tube of 50 SN74HC20D.
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