SN74LVC2G08-Q1 Gate Datasheet

SN74LVC2G08-Q1 Datasheet, PDF, Equivalent


Part Number

SN74LVC2G08-Q1

Description

Dual 2-Input Positive-AND Gate

Manufacture

etcTI

Total Page 10 Pages
Datasheet
Download SN74LVC2G08-Q1 Datasheet


SN74LVC2G08-Q1
SN74LVC2G08-Q1
www.ti.com
SCES557D – MARCH 2004 – REVISED MARCH 2010
DUAL 2-INPUT POSITIVE-AND GATE
Check for Samples: SN74LVC2G08-Q1
FEATURES
1
• Qualified for Automotive Applications
• Supports 5-V VCC Operation
• Inputs Accept Voltages to 5.5 V
• Max tpd of 4.7 ns at 3.3 V
• Low Power Consumption, 10-μA Max ICC
• ±24-mA Output Drive at 3.3 V
• Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
• Ioff Supports Partial-Power-Down Mode
Operation
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
DCT Package
(Top View)
1A
1B
2Y
GND
1
2
3
4
8 VCC
7 1Y
6 2B
5 2A
P0147-01
DESCRIPTION/ORDERING INFORMATION
This dual 2-input positive-AND gate is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC2G08-Q1 performs the Boolean function Y + A B or Y + A ) B in positive logic.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
TA
–40°C to 85°C
SSOP – DCT
ORDERING INFORMATION(1)
PACKAGE (2)
ORDERABLE PART NUMBER
Tape and reel
SN74LVC2G08IDCTRQ1
TOP-SIDE MARKING(3)
C08_ _ _
(1) For the most-current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) DCT: The actual top-side marking has three additional characters that designate the year, month, and wafer fab/assembly site.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2010, Texas Instruments Incorporated

SN74LVC2G08-Q1
SN74LVC2G08-Q1
SCES557D – MARCH 2004 – REVISED MARCH 2010
FUNCTION TABLE
(EACH GATE)
INPUTS
AB
OUTPUT
Y
HH
H
LX
L
XL
L
LOGIC DIAGRAM (POSITIVE LOGIC)
1
1A
2
1B
7
1Y
5
2A
6
2B
3
2Y
www.ti.com
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage range
VI Input voltage range(2)
VO Voltage range applied to any output in the high-impedance or power-off state(2)
VO Voltage range applied to any output in the high or low state(2) (3)
IIK Input clamp current
VI < 0
IOK Output clamp current
VO < 0
IO Continuous output current
Continuous current through VCC or GND
θJA Package thermal impedance(4)
DCT package
Tstg Storage temperature range
–0.5
–0.5
–0.5
–0.5
–65
6.5
6.5
6.5
VCC + 0.5
–50
–50
±50
±100
220
150
V
V
V
V
mA
mA
mA
mA
°C/W
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the Recommended Operating Conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
2 Submit Documentation Feedback
Copyright © 2004–2010, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC2G08-Q1


Features SN74LVC2G08-Q1 www.ti.com SCES557D – MARCH 2004 – REVISED MARCH 2010 DUA L 2-INPUT POSITIVE-AND GATE Check for S amples: SN74LVC2G08-Q1 FEATURES 1 • Qualified for Automotive Applications Supports 5-V VCC Operation • Input s Accept Voltages to 5.5 V • Max tpd of 4.7 ns at 3.3 V • Low Power Consum ption, 10-μA Max ICC • ±24-mA Outpu t Drive at 3.3 V • Typical VOLP (Outp ut Ground Bounce) <0.8 V at VCC = 3.3 V , TA = 25°C • Typical VOHV (Output V OH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C • Ioff Supports Partial-Powe r-Down Mode Operation • Latch-Up Perf ormance Exceeds 100 mA Per JESD 78, Cla ss II • ESD Protection Exceeds JESD 2 2 – 2000-V Human-Body Model (A114-A) – 1000-V Charged-Device Model (C101) DCT Package (Top View) 1A 1B 2Y GND 1 2 3 4 8 VCC 7 1Y 6 2B 5 2A P0147-01 DESCRIPTION/ORDERING INFORMATION This dual 2-input positive-AND gate is desi gned for 1.65-V to 5.5-V VCC operation. The SN74LVC2G08-Q1 performs the Boolean function Y + A • B or Y + A ) B in positive logic. This .
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