SN74LVC2G125-Q1 Gate Datasheet

SN74LVC2G125-Q1 Datasheet, PDF, Equivalent


Part Number

SN74LVC2G125-Q1

Description

Dual Bus Buffer Gate

Manufacture

etcTI

Total Page 14 Pages
Datasheet
Download SN74LVC2G125-Q1 Datasheet


SN74LVC2G125-Q1
SN74LVC2G125-Q1
www.ti.com
DUAL BUS BUFFER GATE
WITH 3-STATE OUTPUTS
Check for Samples: SN74LVC2G125-Q1
SCES559C MARCH 2004 REVISED MARCH 2011
FEATURES
1
Qualified for Automotive Applications
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 4.3 ns at 3.3 V
Low Power Consumption, 10-μA Max ICC
• ±24-mA Output Drive at 3.3 V
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
DCT OR DCU PACKAGE
(TOP VIEW)
1OE
1A
2Y
GND
1
2
3
4
8 VCC
7 2OE
6 1Y
5 2A
DESCRIPTION/ORDERING INFORMATION
The SN74LVC2G125-Q1 is a dual bus buffer gate designed for 1.65-V to 5.5-V VCC operation. This device
features dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE)
input is high.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
TA
40°C to 85°C
SSOP DCT
VSSOP DCU
ORDERING INFORMATION(1)
PACKAGE (2)
ORDERABLE PART NUMBER
Tape and reel
CLVC2G125IDCTRQ1
Tape and reel
CLVC2G125IDCURQ1
TOP-SIDE MARKING(3)
C25_ _ _
CCW_
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
FUNCTION TABLE
(EACH BUFFER)
INPUTS
OE A
OUTPUT
Y
LH
H
LL
L
HX
Z
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 20042011, Texas Instruments Incorporated

SN74LVC2G125-Q1
SN74LVC2G125-Q1
SCES559C MARCH 2004 REVISED MARCH 2011
LOGIC DIAGRAM (POSITIVE LOGIC)
1
1OE
2
1A
6
1Y
7
2OE
5
2A
3
2Y
www.ti.com
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage range
VI Input voltage range(2)
VO Voltage range applied to any output in the high-impedance or power-off state(2)
VO Voltage range applied to any output in the high or low state(2) (3)
IIK Input clamp current
VI < 0
IOK Output clamp current
VO < 0
IO Continuous output current
Continuous current through VCC or GND
θJA Package thermal impedance(4)
DCT package
DCU package
0.5
0.5
0.5
0.5
6.5
6.5
6.5
VCC + 0.5
50
50
±50
±100
220
227
V
V
V
V
mA
mA
mA
mA
°C/W
Tstg Storage temperature range
65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
2 Submit Documentation Feedback
Copyright © 20042011, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC2G125-Q1


Features SN74LVC2G125-Q1 www.ti.com DUAL BUS BU FFER GATE WITH 3-STATE OUTPUTS Check fo r Samples: SN74LVC2G125-Q1 SCES559C MARCH 2004 – REVISED MARCH 2011 FE ATURES 1 • Qualified for Automotive A pplications • Supports 5-V VCC Operat ion • Inputs Accept Voltages to 5.5 V • Max tpd of 4.3 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Typic al VOLP (Output Ground Bounce) <0.8 V a t VCC = 3.3 V, TA = 25°C • Typical V OHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C • Ioff Supports Partial-Power-Down Mode Operation • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II DCT OR DCU PACKAGE (TOP VIEW) 1OE 1A 2Y GND 1 2 3 4 8 V CC 7 2OE 6 1Y 5 2A DESCRIPTION/ORDERIN G INFORMATION The SN74LVC2G125-Q1 is a dual bus buffer gate designed for 1.65- V to 5.5-V VCC operation. This device f eatures dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is high. To ensure the high-impedance state during .
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