SN74LVC2G126-EP Gate Datasheet

SN74LVC2G126-EP Datasheet, PDF, Equivalent


Part Number

SN74LVC2G126-EP

Description

Dual Bus Buffer Gate

Manufacture

etcTI

Total Page 13 Pages
Datasheet
Download SN74LVC2G126-EP Datasheet


SN74LVC2G126-EP
SN74LVC2G126-EP
www.ti.com
SCES856 – DECEMBER 2013
DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS
Check for Samples: SN74LVC2G126-EP
FEATURES
1
• Supports 5-V VCC Operation
• Inputs Accept Voltages to 5.5 V
• Max tpd of 6.8 ns at 3.3 V
• Low Power Consumption, 10-μA Max ICC
• ±24-mA Output Drive at 3.3 V
• Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
• Ioff Supports Partial-Power-Down Mode
Operation
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
• Controlled Baseline
• One Assembly and Test Site
• One Fabrication Site
• Available in Military (–55°C to 125°C)
Temperature Range
• Extended Product Life Cycle
• Extended Product-Change Notification
• Product Traceability
DCU PACKAGE
(TOP VIEW)
1OE
1A
2Y
GND
1
2
3
4
8 VCC
7 2OE
6 1Y
5 2A
DESCRIPTION
This dual bus buffer gate is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC2G126 is a dual bus driver/line driver with 3-state outputs. The outputs are disabled when the
associated output-enable (OE) input is low.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
TJ
–55°C to 125°C
ORDERING INFORMATION(1)
PACKAGE (2)
ORDERABLE PART NUMBER
VSSOP - DCU Tape of 250
CLVC2G126MDCUTEP
TOP-SIDE MARKING
CEPR
VID NUMBER
V62/14604-01XE
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Function Table
(Each Buffer)
INPUTS
OE A
OUTPUT
Y
HH
H
HL
L
LX
Z
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated

SN74LVC2G126-EP
SN74LVC2G126-EP
SCES856 – DECEMBER 2013
Logic Diagram (Positive Logic)
1
1OE
2
1A
6
1Y
7
2OE
5
2A
3
2Y
www.ti.com
ABSOLUTE MAXIMUM RATINGs(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage range
VI Input voltage range(2)
VO Voltage range applied to any output in the high-impedance or power-off state(2)
VO Voltage range applied to any output in the high or low state(2) (3)
IIK Input clamp current
VI < 0
IOK Output clamp current
VO < 0
IO Continuous output current
Continuous current through VCC or GND
TJ Absolute maximum junction temperature range
Tstg Storage temperature range
–0.5
–0.5
–0.5
–0.5
–55
–65
6.5
6.5
6.5
VCC + 0.5
–50
–50
±50
±100
150
150
V
V
V
V
mA
mA
mA
mA
°C
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
THERMAL INFORMATION
THERMAL METRIC(1)
SN74LVC2G126-EP
DCU
UNITS
θJA
θJCtop
θJB
ψJT
ψJB
θJCbot
Junction-to-ambient thermal resistance(2)
Junction-to-case (top) thermal resistance(3)
Junction-to-board thermal resistance(4)
Junction-to-top characterization parameter(5)
Junction-to-board characterization parameter(6)
Junction-to-case (bottom) thermal resistance(7)
8 PINS
204.3
78
83
7.6
82.6
N/A
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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Features SN74LVC2G126-EP www.ti.com SCES856 – DECEMBER 2013 DUAL BUS BUFFER GATE WI TH 3-STATE OUTPUTS Check for Samples: S N74LVC2G126-EP FEATURES 1 • Supports 5-V VCC Operation • Inputs Accept Vo ltages to 5.5 V • Max tpd of 6.8 ns a t 3.3 V • Low Power Consumption, 10- A Max ICC • ±24-mA Output Drive at 3.3 V • Typical VOLP (Output Ground B ounce) <0.8 V at VCC = 3.3 V, TA = 25° C • Typical VOHV (Output VOH Undersho ot) >2 V at VCC = 3.3 V, TA = 25°C • Ioff Supports Partial-Power-Down Mode Operation • Latch-Up Performance Exce eds 100 mA Per JESD 78, Class II • ES D Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Ma chine Model (A115-A) – 1000-V Charged -Device Model (C101) SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS Controlled Baseline • One Assembly and Test Site • One Fabrication Site • Available in Military (–55°C to 125°C) Temperature Range • Extended Product Life Cycle • Extended Product-Change Notification • Product Traceability DCU PACKAGE (TOP VIEW) 1OE.
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