SN74LVC2G126-EP

SN74LVC2G126-EP www.ti.com SCES856 – DECEMBER 2013 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS Check for Samples: SN74LVC2G126-EP FEATURES 1 Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 6.8 ns at 3.3 V Low Power Consumption, 10-μA Max ICC ±24-mA Output Drive at 3.3 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS Controlled Baseline One Assembly and Test Site One Fabrication Site Available in Military (–55°C to 125°C) Temperature Range Extended Product Life Cycle Extended Product-Change Notification Product Traceability DCU PACKAGE (TOP VIEW) 1OE 1A 2Y GND 1 2 3 4 8 VCC 7 2OE 6 1Y 5 2A DESCRIPTION This dual bus buffer gate is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC2G126 is a dual bus driver/line driver with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is low. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. Thi...