SN74LVC2G17-EP Buffer Datasheet

SN74LVC2G17-EP Datasheet, PDF, Equivalent


Part Number

SN74LVC2G17-EP

Description

Dual Schmitt-Trigger Buffer

Manufacture

etcTI

Total Page 12 Pages
Datasheet
Download SN74LVC2G17-EP Datasheet


SN74LVC2G17-EP
www.ti.com
FEATURES
Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
Enhanced Diminishing Manufacturing Sources
(DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree (1)
Customer-Specific Configuration Control Can
Be Supported Along With Major-Change
Approval
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 5.4 ns at 3.3 V
Low Power Consumption, 10-µA Max ICC
• ±24-mA Output Drive at 3.3 V
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
SN74LVC2G17-EP
DUAL SCHMITT-TRIGGER BUFFER
SCES683 – JANUARY 2007
Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
DCK PACKAGE
(TOP VIEW)
1A 1 6 1Y
GND 2 5 VCC
2A 3 4 2Y
DESCRIPTION/ORDERING INFORMATION
This dual Schmitt-trigger buffer is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC2G17 contains two buffers and performs the Boolean function Y = A. The device functions as two
independent buffers, but because of Schmitt action, it may have different input threshold levels for positive-going
(VT+) and negative-going (VT–) signals.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
–55°C to 125°C
PACKAGE (1)
SOT (SC-70) – DCK
Reel of 3000
ORDERABLE PART NUMBER TOP-SIDE MARKING(2)
SN74LVC2G17MDCKREP
BZV
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DCK: The actual top-side marking has one additional character that designates the assembly/test site. Pin 1 identifier indicates
solder-bump composition (1 = SnPb, = Pb-free).
FUNCTION TABLE
(EACH INVERTER)
INPUT
A
H
L
OUTPUT
Y
H
L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated

SN74LVC2G17-EP
SN74LVC2G17-EP
DUAL SCHMITT-TRIGGER BUFFER
SCES683 – JANUARY 2007
LOGIC DIAGRAM (POSITIVE LOGIC)
1
1A
6
1Y
3
2A
4
2Y
www.ti.com
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
VCC Supply voltage range
VI Input voltage range(2)
VO Voltage range applied to any output in the high-impedance or power-off state(2)
VO Voltage range applied to any output in the high or low state(2)(3)
IIK Input clamp current
VI < 0
IOK Output clamp current
VO < 0
IO Continuous output current
Continuous current through VCC or GND
θJA Package thermal impedance(4)
DBV package
DCK package
Tstg Storage temperature range
MIN
–0.5
–0.5
–0.5
–0.5
–65
MAX
6.5
6.5
6.5
VCC + 0.5
–50
–50
±50
±100
165
259
150
UNIT
V
V
V
V
mA
mA
mA
mA
°C/W
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)(2)
VCC Supply voltage
VI Input voltage
VO Output voltage
IOH High-level output current
IOL Low-level output current
TA Operating free-air temperature
Operating
VCC = 1.65 V
VCC = 2.3 V
VCC = 3 V
VCC = 4.5 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 3 V
VCC = 4.5 V
MIN
1.65
0
0
–55
MAX
5.5
5.5
VCC
–4
–8
–16
–24
–32
4
8
16
24
32
125
UNIT
V
V
V
mA
mA
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
(2) Long-term high-temperature storage and/or extended use at maximum recommended operating conditions may result in a reduction of
overall device life. See http://www.ti.com/ep_quality for additional information on enhanced plastic packaging.
2 Submit Documentation Feedback


Features www.ti.com FEATURES • Controlled Basel ine – One Assembly/Test Site, One Fab rication Site • Enhanced Diminishing Manufacturing Sources (DMS) Support • Enhanced Product-Change Notification Qualification Pedigree (1) • Custo mer-Specific Configuration Control Can Be Supported Along With Major-Change Ap proval • Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V • Max tpd of 5.4 ns at 3.3 V • Low Powe r Consumption, 10-µA Max ICC • ±24- mA Output Drive at 3.3 V • Typical VO LP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C (1) Component qual ification in accordance with JEDEC and industry standards to ensure reliable o peration over an extended temperature r ange. This includes, but is not limited to, Highly Accelerated Stress Test (HA ST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromig ration, bond intermetallic life, and mo ld compound life. Such qualification te sting should not be viewed as justifying use of this component beyond specified performanc.
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