SN74LVC2G17-Q1 Buffer Datasheet

SN74LVC2G17-Q1 Datasheet, PDF, Equivalent


Part Number

SN74LVC2G17-Q1

Description

Dual Schmitt-Trigger Buffer

Manufacture

etcTI

Total Page 12 Pages
Datasheet
Download SN74LVC2G17-Q1 Datasheet


SN74LVC2G17-Q1
SN74LVC2G17-Q1
www.ti.com.................................................................................................................................................... SCES618B – OCTOBER 2004 – REVISED APRIL 2008
DUAL SCHMITT-TRIGGER BUFFER
FEATURES
1
Qualified for Automotive Applications
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 5.4 ns at 3.3 V
Low Power Consumption, 10-µA Max ICC
±24-mA Output Drive at 3.3 V
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
1A
GND
1
2
6 1Y
1A 1 6 1Y
GND 2 5 VCC
5 VCC 2A 3 4 2Y
2A 3
4 2Y
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This dual Schmitt-trigger buffer is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC2G17 contains two buffers and performs the Boolean function Y = A. The device functions as two
independent buffers, but because of Schmitt action, it may have different input threshold levels for positive-going
(VT+) and negative-going (VT–) signals.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
TA
–40°C to 125°C
ORDERING INFORMATION(1)
PACKAGE (2)
ORDERABLE PART NUMBER TOP-SIDE MARKING(3)
SOT (SOT-23) – DBV
Reel of 3000 SN74LVC2G17QDBVRQ1
C17_
SOT (SC-70) – DCK
Reel of 3000 SN74LVC2G17QDCKRQ1
C7_
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) DBV/DCK: The actual top-side marking has one additional character that designates the wafer fab/assembly site. Pin 1 identifier
indicates solder-bump composition (1 = SnPb, • = Pb-free).
FUNCTION TABLE
(EACH INVERTER)
INPUT
A
H
L
OUTPUT
Y
H
L
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2008, Texas Instruments Incorporated

SN74LVC2G17-Q1
SN74LVC2G17-Q1
SCES618B – OCTOBER 2004 – REVISED APRIL 2008.................................................................................................................................................... www.ti.com
LOGIC DIAGRAM (POSITIVE LOGIC)
1
1A
6
1Y
3
2A
4
2Y
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
VCC Supply voltage range
VI Input voltage range(2)
VO Voltage range applied to any output in the high-impedance or power-off state(2)
VO Voltage range applied to any output in the high or low state(2)(3)
IIK Input clamp current
VI < 0
IOK Output clamp current
VO < 0
IO Continuous output current
Continuous current through VCC or GND
θJA Package thermal impedance(4)
DBV package
DCK package
Tstg Storage temperature range
MIN MAX UNIT
–0.5 6.5 V
–0.5 6.5 V
–0.5 6.5 V
–0.5
VCC + 0.5
–50
V
mA
–50 mA
±50 mA
±100 mA
165
°C/W
259
–65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)
VCC Supply voltage
VI Input voltage
VO Output voltage
IOH High-level output current
IOL Low-level output current
TA Operating free-air temperature
Operating
VCC = 1.65 V
VCC = 2.3 V
VCC = 3 V
VCC = 4.5 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 3 V
VCC = 4.5 V
MIN
1.65
0
0
–40
MAX
5.5
5.5
VCC
–4
–8
–16
–24
–32
4
8
16
24
32
125
UNIT
V
V
V
mA
mA
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2 Submit Documentation Feedback
Copyright © 2004–2008, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC2G17-Q1


Features SN74LVC2G17-Q1 www.ti.com.............. ....................................... ....................................... ....................................... ................. SCES618B – OCTOBER 2004 – REVISED APRIL 2008 DUAL SCHMIT T-TRIGGER BUFFER FEATURES 1 • Qualif ied for Automotive Applications • Sup ports 5-V VCC Operation • Inputs Acce pt Voltages to 5.5 V • Max tpd of 5.4 ns at 3.3 V • Low Power Consumption, 10-µA Max ICC • ±24-mA Output Driv e at 3.3 V • Typical VOLP (Output Gro und Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C • Typical VOHV (Output VOH Und ershoot) >2 V at VCC = 3.3 V, TA = 25° C • Ioff Supports Partial-Power-Down Mode Operation • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2 000-V Human-Body Model (A114-A) – 100 0-V Charged-Device Model (C101) DBV PA CKAGE (TOP VIEW) DCK PACKAGE (TOP VIEW ) 1A GND 1 2 6 1Y 1A 1 6 1Y GND 2 5 VCC 5 VCC 2A 3 4 2Y 2A 3 4 2Y See mechanical drawings for dimensions. DESCRIPTION/ORDERING .
Keywords SN74LVC2G17-Q1, datasheet, pdf, etcTI, Dual, Schmitt-Trigger, Buffer, N74LVC2G17-Q1, 74LVC2G17-Q1, 4LVC2G17-Q1, SN74LVC2G17-Q, SN74LVC2G17-, SN74LVC2G17, Equivalent, stock, pinout, distributor, price, schematic, inventory, databook, Electronic, Components, Parameters, parts, cross reference, chip, Semiconductor, circuit, Electric, manual, substitute




@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)