SN74LVC2G32 Gate Datasheet

SN74LVC2G32 Datasheet, PDF, Equivalent


Part Number

SN74LVC2G32

Description

Dual 2-Input Positive-OR Gate

Manufacture

etcTI

Total Page 24 Pages
Datasheet
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SN74LVC2G32
SCES201N – APRIL 1999 – REVISED SEPTEMBER 2015
SN74LVC2G32 Dual 2-Input Positive-OR Gate
1 Features
1 Available in the Texas Instruments
NanoFree™ Package
• Supports 5-V VCC Operation
• Inputs Accept Voltages to 5.5 V
• Maximum tpd of 3.8 ns at 3.3 V
• Low Power Consumption, 10-µA Maximum ICC
• ±24-mA Output Drive at 3.3 V
• Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
• Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
• Can Be Used as a Down Translator to Translate
Inputs From a Maximum of 5.5 V Down to the VCC
Level
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
3 Description
This dual 2-input positive-OR gate is designed for
1.65-V to 5.5-V VCC operation.
The SN74LVC2G32 device performs the Boolean
function Y + A ) B or Y + A B in positive logic.
NanoFree package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE
SN74LVC2G32DCT SSOP (8)
2.95 mm × 2.80 mm
SN74LVC2G32DCU VSSOP (8)
2.30 mm × 2.00 mm
SN74LVC2G32YZP DSBGA (8)
1.91 mm × 0.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
• Down Translation
• Logical OR
Logic Diagram (Positive Logic)
1
1A
2
1B
7
1Y
5
2A
6
2B
3
2Y
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

SN74LVC2G32
SN74LVC2G32
SCES201N – APRIL 1999 – REVISED SEPTEMBER 2015
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ..................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions ...................... 5
6.4 Thermal Information .................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Switching Characteristics .......................................... 6
6.7 Operating Characteristics.......................................... 6
6.8 Typical Characteristics .............................................. 7
7 Parameter Measurement Information .................. 8
8 Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................... 9
8.4 Device Functional Modes.......................................... 9
9 Application and Implementation ........................ 10
9.1 Application Information............................................ 10
9.2 Typical Application ................................................. 10
10 Power Supply Recommendations ..................... 11
11 Layout................................................................... 11
11.1 Layout Guidelines ................................................. 11
11.2 Layout Example .................................................... 11
12 Device and Documentation Support ................. 12
12.1 Related Documentation......................................... 12
12.2 Community Resources.......................................... 12
12.3 Trademarks ........................................................... 12
12.4 Electrostatic Discharge Caution ............................ 12
12.5 Glossary ................................................................ 12
13 Mechanical, Packaging, and Orderable
Information ........................................................... 12
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision M (November 2013) to Revision N
Page
• Added Applications section, Device Information table, Pin Configuration and Functions section, ESD Ratings table,
Thermal Information table, Typical Characteristics section, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section ..................................... 1
Changes from Revision L (February 2007) to Revision M
Page
• Updated document to new TI data sheet format. ................................................................................................................... 1
• Removed Ordering Information table. .................................................................................................................................... 1
• Updated Features. .................................................................................................................................................................. 1
• Updated operating temperature range. .................................................................................................................................. 5
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Copyright © 1999–2015, Texas Instruments Incorporated
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Features Product Folder Sample & Buy Technical Documents Tools & Software Support & Community SN74LVC2G32 SCES201N – APR IL 1999 – REVISED SEPTEMBER 2015 SN74 LVC2G32 Dual 2-Input Positive-OR Gate 1 Features •1 Available in the Texas Instruments NanoFree™ Package • Sup ports 5-V VCC Operation • Inputs Acce pt Voltages to 5.5 V • Maximum tpd of 3.8 ns at 3.3 V • Low Power Consumpt ion, 10-µA Maximum ICC • ±24-mA Out put Drive at 3.3 V • Typical VOLP (Ou tput Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C • Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, T A = 25°C • Ioff Supports Live Insert ion, Partial-Power-Down Mode, and Back- Drive Protection • Can Be Used as a D own Translator to Translate Inputs From a Maximum of 5.5 V Down to the VCC Lev el • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II • ESD Prote ction Exceeds JESD 22 – 2000-V Human Body Model (A114-A) – 1000-V Charged- Device Model (C101) 3 Description This dual 2-input positive-OR gate is designed for 1.65-V to 5.5-V.
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