SN74LVC2G32-Q1 Gate Datasheet

SN74LVC2G32-Q1 Datasheet, PDF, Equivalent


Part Number

SN74LVC2G32-Q1

Description

Dual 2-Input Positive-OR Gate

Manufacture

etcTI

Total Page 12 Pages
Datasheet
Download SN74LVC2G32-Q1 Datasheet


SN74LVC2G32-Q1
SN74LVC2G32-Q1
www.ti.com
SCES842 – AUGUST 2012
DUAL TWO-INPUT POSITIVE-OR GATE
Check for Samples: SN74LVC2G32-Q1
FEATURES
1
2 Qualified for Automotive Applications
• AEC-Q100 Qualified With the Following
Results:
– Device Temperature Grade 1: –40°C to
125°C Ambient Operating Temperature
Range
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C3B
• Inputs Accept Voltages to 5.5 V
• Max Propagation (Delay) Time of 3.8 ns at 3.3
V
• Low Power Consumption, 10-μA Max Supply
Current
• ±24-mA Output Drive at 3.3 V
• Typical Voltage Output Low Peak (Output
Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
• Typical Voltage Output High Valley (VOH
Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
• Ioff State Current Supports Partial-Power-Down
Mode Operation
APPLICATIONS
• Automotive
• Logic and Gates
1A
1B
2Y
GND
DCU PACKAGE
(TOP VIEW)
18
27
36
45
VCC
1Y
2B
2A
DESCRIPTION
This dual two-input positive-OR gate is designed for 1.65-V to 5.5-V collector supply voltage operation.
The SN74LVC2G32-Q1 performs the Boolean function Y + A ) B or Y + A B in positive logic.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using the off-state current. The off-state current
circuitry disables the outputs, preventing damaging current backflow through the device when it is powered
down.
TA
–40°C to 125°C
ORDERING INFORMATION(1)
PACKAGE (2)
ORDERABLE PART NUMBER
VSSOP - DCU
Reel of 3000
SN74LVC2G32QDCURQ1
TOP-SIDE MARKING
SUCQ
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012, Texas Instruments Incorporated

SN74LVC2G32-Q1
SN74LVC2G32-Q1
SCES842 – AUGUST 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
FUNCTION TABLE
(EACH GATE)
INPUTS
AB
OUTPUT
Y
HX
H
XH
H
LL
L
LOGIC DIAGRAM (POSITIVE LOGIC)
1
1A
2
1B
7
1Y
5
2A
6
2B
3
2Y
ABSOLUTE MAXIMUM RATINGS(1)
over operating free-air temperature range (unless otherwise noted)
VCC Supply voltage range
VI Input voltage range(2)
VO Voltage range applied to any output in the high-impedance or power-off state(2)
VO Voltage range applied to any output in the high or low state(2) (3)
IIK Input clamp current
VI < 0
IOK Output clamp current VO < 0
IO Continuous output current
Continuous current through VCC or GND
Tstg Storage temperature range
ESD Rating
Human body model (HBM) AEC-Q100 classification level H2
Charged device model (CDM) AEC-Q100 classification level C3B
MIN MAX UNIT
–0.5 6.5 V
–0.5 6.5 V
–0.5 6.5 V
–0.5 VCC + 0.5 V
–50 mA
–50 mA
±50 mA
±100 mA
–65 150 °C
2 kV
750 V
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
THERMAL INFORMATION
THERMAL METRIC(1)
θJA
θJCtop
θJB
ψJT
ψJB
θJCbot
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
SN74LVC2G32-Q1
DCU (8 PINS)
204.4
77
83.2
7.1
82.7
N/A
UNIT
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
2 Submit Documentation Feedback
Copyright © 2012, Texas Instruments Incorporated
Product Folder Links: SN74LVC2G32-Q1


Features SN74LVC2G32-Q1 www.ti.com SCES842 – AUGUST 2012 DUAL TWO-INPUT POSITIVE-OR GATE Check for Samples: SN74LVC2G32-Q1 FEATURES 1 •2 Qualified for Automot ive Applications • AEC-Q100 Qualified With the Following Results: – Device Temperature Grade 1: –40°C to 125° C Ambient Operating Temperature Range Device HBM ESD Classification Level H2 – Device CDM ESD Classification Le vel C3B • Inputs Accept Voltages to 5 .5 V • Max Propagation (Delay) Time o f 3.8 ns at 3.3 V • Low Power Consump tion, 10-μA Max Supply Current • ±2 4-mA Output Drive at 3.3 V • Typical Voltage Output Low Peak (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 2 5°C • Typical Voltage Output High Va lley (VOH Undershoot) > 2 V at VCC = 3. 3 V, TA = 25°C • Ioff State Current Supports Partial-Power-Down Mode Operat ion APPLICATIONS • Automotive • Lo gic and Gates 1A 1B 2Y GND DCU PACKAG E (TOP VIEW) 18 27 36 45 VCC 1Y 2B 2A DESCRIPTION This dual two-input positive-OR gate is designed for 1.65-V to 5.5-V collector supply vo.
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