SN74LVC2G34-EP Gate Datasheet

SN74LVC2G34-EP Datasheet, PDF, Equivalent


Part Number

SN74LVC2G34-EP

Description

Dual Buffer Gate

Manufacture

etcTI

Total Page 12 Pages
Datasheet
Download SN74LVC2G34-EP Datasheet


SN74LVC2G34-EP
www.ti.com
FEATURES
Controlled Baseline
– One Assembly Site
– One Test Site
– One Fabrication Site
Extended Temperature Performance of –55°C
to 125°C
Enhanced Diminishing Manufacturing Sources
(DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree (1)
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
SN74LVC2G34-EP
DUAL BUFFER GATE
SCES671 – MARCH 2007
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 4.1 ns at 3.3 V
Low-Power Consumption, 10-µA Max ICC
• ±24-mA Output Drive at 3.3 V
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DCK PACKAGE
(TOP VIEW)
1A 1 6 1Y
GND 2 5 VCC
2A 3 4 2Y
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
The SN74LVC2G34 is a dual buffer gate designed for 1.65-V to 5.5-V VCC operation. The SN74LVC2G34
performs the Boolean function Y = A in positive logic.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION(1)
TA
–55°C to 125°C
PACKAGE (2)
SOT (SC-70) – DCK
Reel of 3000
ORDERABLE PART NUMBER
SN74LVC2G34MDCKREP
TOP-SIDE MARKING(3)
CAZ
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(3) The actual top-side marking has one additional character that designates the assembly/test site.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2007, Texas Instruments Incorporated

SN74LVC2G34-EP
SN74LVC2G34-EP
DUAL BUFFER GATE
SCES671 – MARCH 2007
FUNCTION TABLE
(EACH GATE)
INPUT
A
H
L
OUTPUT
Y
H
L
LOGIC DIAGRAM (POSITIVE LOGIC)
1A 1
6 1Y
2A 3
4 2Y
www.ti.com
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
VCC Supply voltage range
VI Input voltage range(2)
VO Voltage range applied to any output in the high-impedance or power-off state(2)
VO Voltage range applied to any output in the high or low state(2)(3)
IIK Input clamp current
VI < 0 V
IOK Output clamp current
VO < 0 V
IO Continuous output current
Continuous current through VCC or GND
θJA Package thermal impedance(4)
DCK package
Tstg Storage temperature range
MIN MAX UNIT
–0.5 6.5 V
–0.5 6.5 V
–0.5 6.5 V
–0.5
VCC + 0.5
–50
V
mA
–50 mA
±50 mA
±100 mA
259 °C/W
–65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
2 Submit Documentation Feedback


Features www.ti.com FEATURES • Controlled Basel ine – One Assembly Site – One Test Site – One Fabrication Site • Exten ded Temperature Performance of –55°C to 125°C • Enhanced Diminishing Man ufacturing Sources (DMS) Support • En hanced Product-Change Notification • Qualification Pedigree (1) (1) Componen t qualification in accordance with JEDE C and industry standards to ensure reli able operation over an extended tempera ture range. This includes, but is not l imited to, Highly Accelerated Stress Te st (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, elec tromigration, bond intermetallic life, and mold compound life. Such qualificat ion testing should not be viewed as jus tifying use of this component beyond sp ecified performance and environmental l imits. SN74LVC2G34-EP DUAL BUFFER GATE SCES671 – MARCH 2007 • Supports 5- V VCC Operation • Inputs Accept Volta ges to 5.5 V • Max tpd of 4.1 ns at 3 .3 V • Low-Power Consumption, 10-µA Max ICC • ±24-mA Output Drive at 3.3 V • Typical VOLP (.
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