SN74LVC2G38 Gate Datasheet

SN74LVC2G38 Datasheet, PDF, Equivalent


Part Number

SN74LVC2G38

Description

Dual 2-Input NAND Gate

Manufacture

etcTI

Total Page 19 Pages
Datasheet
Download SN74LVC2G38 Datasheet


SN74LVC2G38
www.ti.com
SN74LVC2G38
SCES554D – MARCH 2004 – REVISED DECEMBER 2013
Dual 2-Input NAND Gate With Open-Drain Outputs
Check for Samples: SN74LVC2G38
FEATURES
1
2 Available in the Texas Instruments NanoFree™
Package
• Supports 5-V VCC Operation
• Inputs Accept Voltages to 5.5 V
• Max tpd of 4 ns at 3.3 V
• Low Power Consumption, 10-μA Max ICC
• ±24-mA Output Drive at 3.3 V
• Typical VOLP (Output Ground Bounce) <0.8 V at
VCC = 3.3 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
• Ioff Supports Live insertion, Partial-Power-
Down Mode Operation and Back Drive
Protection
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION
The SN74LVC2G38 is designed for 1.65-V to 5.5-V
VCC operation.
This device is a dual two-input NAND buffer gate with
open-drain outputs. It performs the Boolean function
Y = A • B or Y = A + B in positive logic.
NanoFree™ package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
1A
1B
2Y
GND
DCT PACKAGE
(TOP VIEW)
18
27
36
45
VCC
1Y
2B
2A
DCU PACKAGE
(TOP VIEW)
1A
1B
2Y
GND
1
2
3
4
8 VCC
7 1Y
6 2B
5 2A
YZP PACKAGE
(BOTTOM VIEW)
GND 4 5 2A
2Y 3 6 2B
1B 2 7 1Y
1A 1 8 VCC
See mechanical drawings for dimensions.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2013, Texas Instruments Incorporated

SN74LVC2G38
SN74LVC2G38
SCES554D – MARCH 2004 – REVISED DECEMBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Function Table
(Each Gate)
INPUTS
AB
OUTPUT
Y
LL
H
LH
H
HL
H
HH
L
Logic Diagram (Positive Logic)
1
1A
2
1B
7
1Y
5
2A
6
2B
3
2Y
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
VCC Supply voltage range
VI Input voltage range(2)
VO Voltage range applied to any output in the high-impedance or power-off state(2)
VO Voltage range applied to any output in the high or low state(2) (3)
IIK Input clamp current
VI < 0
IOK Output clamp current
VO < 0
IO Continuous output current
Continuous current through VCC or GND
DCT package
θJA Package thermal impedance(4)
DCU package
YZP package
Tstg Storage temperature range
MIN
–0.5
–0.5
–0.5
–0.5
–65
MAX
6.5
6.5
6.5
VCC + 0.5
–50
–50
±50
±100
220
227
102
150
UNIT
V
V
V
V
mA
mA
mA
mA
°C/W
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
2 Submit Documentation Feedback
Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links :SN74LVC2G38


Features www.ti.com SN74LVC2G38 SCES554D – MAR CH 2004 – REVISED DECEMBER 2013 Dual 2-Input NAND Gate With Open-Drain Outp uts Check for Samples: SN74LVC2G38 FEA TURES 1 •2 Available in the Texas Ins truments NanoFree™ Package • Suppor ts 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Max tpd of 4 ns a t 3.3 V • Low Power Consumption, 10- A Max ICC • ±24-mA Output Drive at 3.3 V • Typical VOLP (Output Ground B ounce) <0.8 V at VCC = 3.3 V, TA = 25° C • Typical VOHV (Output VOH Undersho ot) >2 V at VCC = 3.3 V, TA = 25°C • Ioff Supports Live insertion, Partial- PowerDown Mode Operation and Back Drive Protection • Latch-Up Performance Ex ceeds 100 mA Per JESD 78, Class II • ESD Protection Exceeds JESD 22 – 2000 -V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charg ed-Device Model (C101) DESCRIPTION The SN74LVC2G38 is designed for 1.65-V to 5.5-V VCC operation. This device is a d ual two-input NAND buffer gate with open-drain outputs. It performs the Boolean function Y = A • B or.
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