SN74LVC2G74-Q1 Flip-Flop Datasheet

SN74LVC2G74-Q1 Datasheet, PDF, Equivalent


Part Number

SN74LVC2G74-Q1

Description

Single Positive-Edge-Triggered D-Type Flip-Flop

Manufacture

etcTI

Total Page 14 Pages
Datasheet
Download SN74LVC2G74-Q1 Datasheet


SN74LVC2G74-Q1
SN74LVC2G74-Q1
www.ti.com ........................................................................................................................................................ SCES563C – MARCH 2004 – REVISED APRIL 2008
SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH CLEAR AND PRESET
FEATURES
1
Qualified for Automotive Applications
Supports 5-V VCC Operation
Inputs Accept Voltages to 5.5 V
Max tpd of 6.9 ns at 3.3 V
Low Power Consumption, 10-µA Max ICC
±24-mA Output Drive at 3.3 V
Typical VOLP (Output Ground Bounce) <0.8 V at
VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot) >2 V at
VCC = 3.3 V, TA = 25°C
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
CLK
D
Q
GND
DCU PACKAGE
(TOP VIEW)
18
27
36
45
VCC
PRE
CLR
Q
DESCRIPTION/ORDERING INFORMATION
This single positive-edge-triggered D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
TA
–40°C to 125°C
ORDERING INFORMATION(1)
PACKAGE (2)
ORDERABLE PART NUMBER
VSSOP – DCU
Reel of 3000
SN74LVC2G74QDCURQ1
TOP-SIDE MARKING(3)
C74_
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) DCU: The actual top-side marking has one additional character that designates the wafer fab/assembly site.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2008, Texas Instruments Incorporated

SN74LVC2G74-Q1
SN74LVC2G74-Q1
SCES563C – MARCH 2004 – REVISED APRIL 2008 ........................................................................................................................................................ www.ti.com
PRE
L
H
L
H
H
H
FUNCTION TABLE
INPUTS
CLR
CLK
HX
LX
LX
H
H
HL
D
X
X
X
H
L
X
OUTPUTS
QQ
HL
L
H (1)
H
H (1)
HL
LH
Q0 Q 0
PRE 7
CLK 1
(1) This configuration is nonstable; that is, it does not persist when PRE
or CLR returns to its inactive (high) level.
LOGIC DIAGRAM (POSITIVE LOGIC)
CC
C
TG
5
Q
D2
C
TG
C
TG
C
C
TG
CLR 6
C
C
3Q
C
2 Submit Documentation Feedback
Copyright © 2004–2008, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC2G74-Q1


Features SN74LVC2G74-Q1 www.ti.com ............. ....................................... ....................................... ....................................... ...................... SCES563C – MAR CH 2004 – REVISED APRIL 2008 SINGLE P OSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET FEATURES 1 • Qualified for Automotive Applications Supports 5-V VCC Operation • Input s Accept Voltages to 5.5 V • Max tpd of 6.9 ns at 3.3 V • Low Power Consum ption, 10-µA Max ICC • ±24-mA Outpu t Drive at 3.3 V • Typical VOLP (Outp ut Ground Bounce) <0.8 V at VCC = 3.3 V , TA = 25°C • Typical VOHV (Output V OH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C • Ioff Supports Partial-Power -Down Mode Operation • Latch-Up Perfo rmance Exceeds 100 mA Per JESD 78, Clas s II • ESD Protection Exceeds JESD 2 2 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 10 00-V Charged-Device Model (C101) CLK D Q GND DCU PACKAGE (TOP VIEW) 18 27 36 45 VCC PRE CLR Q DESCRIPTION/ORDERING INFORMATION This si.
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