SN74LVC2G79 Flip-Flop Datasheet

SN74LVC2G79 Datasheet, PDF, Equivalent


Part Number

SN74LVC2G79

Description

Dual Positive-Edge-Triggered D-Type Flip-Flop

Manufacture

etcTI

Total Page 20 Pages
Datasheet
Download SN74LVC2G79 Datasheet


SN74LVC2G79
SN74LVC2G79
www.ti.com
SCES498E – OCTOBER 2003 – REVISED DECEMBER 2013
Dual Positive-Edge-Triggered D-Type Flip-Flop
Check for Samples: SN74LVC2G79
FEATURES
1
2 Available in the Texas Instruments NanoFree™
Package
• Supports 5-V VCC Operation
• Inputs Accept Voltages to 5.5 V
• Max tpd of 4.2 ns at 3.3 V
• Low Power Consumption, 10-μA Max ICC
• ±24-mA Output Drive at 3.3 V
• Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
• Ioff Feature Supports Live Insertion, Partial-
Power-Down Mode Operation and Back Drive
Protection
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION
This dual positive-edge-triggered D-type flip-flop is
designed for 1.65-V to 5.5-V VCC operation.
When data at the data (D) input meets the setup time
requirement, the data is transferred to the Q output
on the positive-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not directly
related to the rise time of the clock pulse. Following
the hold-time interval, data at the D input can be
changed without affecting the levels at the outputs.
NanoFree™ package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
1CLK
1D
2Q
GND
DCT PACKAGE
(TOP VIEW)
18
27
36
45
VCC
1Q
2D
2CLK
1CLK
1D
2Q
GND
DCU PACKAGE
(TOP VIEW)
18
27
36
45
VCC
1Q
2D
2CLK
YZP PACKAGE
(BOTTOM VIEW)
GND 4 5 2CLK
2Q 3 6 2D
1D 2 7 1Q
1CLK 1 8 VCC
See mechanical drawings for dimensions.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2013, Texas Instruments Incorporated

SN74LVC2G79
SN74LVC2G79
SCES498E – OCTOBER 2003 – REVISED DECEMBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
CLK
L
INPUTS
Function Table
D
H
L
X
OUTPUT
Q
H
L
Q0
Logic Diagram, Each Flip-Flop (Positive Logic)
CLK
CC
C
TG
C
D TG
C
TG
C
C
TG
Q
CC
C
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage range
VI Input voltage range(2)
VO Output voltage range(2)(3)
IIK Input clamp current
VI < 0
IOK Output clamp current
VO < 0
IO Continuous output current
Continuous current through VCC or GND
DCT package
θJA Package thermal impedance(4)
DCU package
YZP package
–0.5
–0.5
–0.5
6.5
6.5
VCC + 0.5
–50
–50
±50
±100
220
227
102
V
V
V
mA
mA
mA
mA
°C/W
Tstg Storage temperature range
–65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
2 Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: SN74LVC2G79


Features SN74LVC2G79 www.ti.com SCES498E – OC TOBER 2003 – REVISED DECEMBER 2013 D ual Positive-Edge-Triggered D-Type Flip -Flop Check for Samples: SN74LVC2G79 F EATURES 1 •2 Available in the Texas I nstruments NanoFree™ Package • Supp orts 5-V VCC Operation • Inputs Accep t Voltages to 5.5 V • Max tpd of 4.2 ns at 3.3 V • Low Power Consumption, 10-μA Max ICC • ±24-mA Output Drive at 3.3 V • Typical VOLP (Output Grou nd Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C • Typical VOHV (Output VOH Unde rshoot) >2 V at VCC = 3.3 V, TA = 25°C • Ioff Feature Supports Live Inserti on, PartialPower-Down Mode Operation an d Back Drive Protection • Latch-Up Pe rformance Exceeds 100 mA Per JESD 78, C lass II • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A ) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DES CRIPTION This dual positive-edge-trigge red D-type flip-flop is designed for 1. 65-V to 5.5-V VCC operation. When data at the data (D) input meets the setup time requirement, the da.
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