SN74LVC2GU04 Gate Datasheet

SN74LVC2GU04 Datasheet, PDF, Equivalent


Part Number

SN74LVC2GU04

Description

Dual Inverter Gate

Manufacture

etcTI

Total Page 19 Pages
Datasheet
Download SN74LVC2GU04 Datasheet


SN74LVC2GU04
SN74LVC2GU04
www.ti.com
SCES197N – APRIL 1999 – REVISED DECEMBER 2013
Dual Inverter Gate
Check for Samples: SN74LVC2GU04
FEATURES
1
2 Available in the Texas Instruments NanoFree™
Package
• Supports 5-V VCC Operation
• Inputs Accept Voltages to 5.5 V
• Max tpd of 3.7 ns at 3.3 V
• Low Power Consumption, 10-µA Max ICC
• ±24-mA Output Drive at 3.3 V
• Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot)
>2 V at VCC = 3.3 V, TA = 25°C
• Ioff Supports Live Insertion, Partial-Power-
Down Mode, and Back-Drive Protection
• Can Be Used as a Down Translator to
Translate Inputs From a Max of 5.5 V Down to
the VCC Level
• Unbuffered Outputs
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION
This dual inverter is designed for 1.65-V to 5.5-V VCC
operation.
The SN74LVC2GU04 device contains two inverters
with unbuffered outputs and performs the Boolean
function Y = A.
NanoFree™ package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
1A 1 6 1Y 1A 1 6 1Y
GND 2 5 VCC
GND
2
5
VCC 2A 3 4 2Y
YZP PACKAGE
(BOTTOM VIEW)
2A
GND
1A
34
25
16
2Y
VCC
1Y
2A 3 4 2Y
See mechanical drawings for dimensions.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2013, Texas Instruments Incorporated

SN74LVC2GU04
SN74LVC2GU04
SCES197N – APRIL 1999 – REVISED DECEMBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Function Table
(Each Inverter)
INPUT
A
OUTPUT
Y
HL
LH
Logic Diagram (Positive Logic)
1
1A
6
1Y
3
2A
4
2Y
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage range
VI Input voltage range(2)
VO Voltage range applied to any output in the high or low state(2)(3)
IIK Input clamp current
VI < 0
IOK Output clamp current
VO < 0
IO Continuous output current
Continuous current through VCC or GND
DBV package
θJA Package thermal impedance(4)
DCK package
YZP package
–0.5
–0.5
–0.5
6.5
6.5
VCC + 0.5
–50
–50
±50
±100
165
259
123
V
V
V
mA
mA
mA
mA
°C/W
Tstg Storage temperature range
–65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
2 Submit Documentation Feedback
Copyright © 1999–2013, Texas Instruments Incorporated
Product Folder Links: SN74LVC2GU04


Features SN74LVC2GU04 www.ti.com SCES197N – A PRIL 1999 – REVISED DECEMBER 2013 Du al Inverter Gate Check for Samples: SN7 4LVC2GU04 FEATURES 1 •2 Available in the Texas Instruments NanoFree™ Pack age • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Max tpd of 3.7 ns at 3.3 V • Low Power C onsumption, 10-µA Max ICC • ±24-mA Output Drive at 3.3 V • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C • Typical VOHV (Out put VOH Undershoot) >2 V at VCC = 3.3 V , TA = 25°C • Ioff Supports Live Ins ertion, Partial-PowerDown Mode, and Bac k-Drive Protection • Can Be Used as a Down Translator to Translate Inputs Fr om a Max of 5.5 V Down to the VCC Level • Unbuffered Outputs • Latch-Up Pe rformance Exceeds 100 mA Per JESD 78, C lass II • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A ) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DES CRIPTION This dual inverter is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC2GU04 device contai.
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