SN74LVC1G386 Gate Datasheet

SN74LVC1G386 Datasheet, PDF, Equivalent


Part Number

SN74LVC1G386

Description

Single 3-Input Positive-XOR Gate

Manufacture

etcTI

Total Page 28 Pages
Datasheet
Download SN74LVC1G386 Datasheet


SN74LVC1G386
SN74LVC1G386
www.ti.com
SCES439E – APRIL 2003 – REVISED DECEMBER 2013
Single 3-Input Positive-XOR Gate
Check for Samples: SN74LVC1G386
FEATURES
1
2 Available in the Texas Instruments
NanoStar ™ and NanoFree™
Packages
• Supports 5-V VCC Operation
• Inputs Accept Voltages to 5.5 V
• Supports Down Translation to VCC
• Ioff Supports Live Insertion, Partial-Power-
Down Mode, Back-Drive Protection
• Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION
The SN74LVC1G386 device performs the Boolean
function Y = A × B × C in positive logic.
NanoStar™ and NanoFree™ package technology is
a major breakthrough in IC packaging concepts,
using the die as the package.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
DBV PACKAGE
(TOP VIEW)
A1
6
GND
2
5
DCK PACKAGE
(TOP VIEW)
C A 1 6C
GND 2 5 VCC
VCC B 3 4 Y
YZP PACKAGE
(BOTTOM VIEW)
B
GND
A
34
25
16
Y
VCC
C
B3 4Y
DRY PACKAGE
(TOP VIEW)
A
GND
B
1
2
3
6C
5 VCC
4Y
See mechanical drawings for dimensions.
DSF PACKAGE
(TOP VIEW)
A1 6 C
GND 2 5 VCC
B3 4 Y
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
2
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2013, Texas Instruments Incorporated

SN74LVC1G386
SN74LVC1G386
SCES439E – APRIL 2003 – REVISED DECEMBER 2013
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Function Table
INPUTS
ABC
OUTPUT
Y
LLL
L
L LH
H
LHL
H
L HH
L
HL L
H
HLH
L
HH L
L
HHH
H
Logic Diagram (Positive Logic)
A
BY
C
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage range
VI Input voltage range(2)
VO Voltage range applied to any output in the high-impedance or power-off state(2)
VO Voltage range applied to any output in the high or low state(2)(3)
IIK Input clamp current
VI < 0
IOK Output clamp current
VO < 0
IO Continuous output current
Continuous current through VCC or GND
DBV package
θJA Package thermal impedance(4)
DCK package
YEP or YZP package
–0.5
–0.5
–0.5
–0.5
6.5
6.5
6.5
VCC + 0.5
–50
–50
±50
±100
165
259
123
V
V
V
V
mA
mA
mA
mA
°C/W
Tstg Storage temperature range
–65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
2 Submit Documentation Feedback
Copyright © 2003–2013, Texas Instruments Incorporated
Product Folder Links: SN74LVC1G386


Features SN74LVC1G386 www.ti.com SCES439E – A PRIL 2003 – REVISED DECEMBER 2013 Si ngle 3-Input Positive-XOR Gate Check fo r Samples: SN74LVC1G386 FEATURES 1 • 2 Available in the Texas Instruments Na noStar ™ and NanoFree™ Packages • Supports 5-V VCC Operation • Inputs Accept Voltages to 5.5 V • Supports D own Translation to VCC • Ioff Support s Live Insertion, Partial-Power- Down M ode, Back-Drive Protection • Latch-Up Performance Exceeds 100 mA Per JESD 78 , Class II • ESD Protection Exceeds J ESD 22 – 2000-V Human-Body Model (A11 4-A) – 200-V Machine Model (A115-A) 1000-V Charged-Device Model (C101) DESCRIPTION The SN74LVC1G386 device per forms the Boolean function Y = A × B C in positive logic. NanoStar™ and NanoFree™ package technology is a maj or breakthrough in IC packaging concept s, using the die as the package. This d evice is fully specified for partial-po wer-down applications using Ioff. The I off circuitry disables the outputs, preventing damaging current backflow through the device when .
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