SN74AUC2G32 GATE Datasheet

SN74AUC2G32 Datasheet, PDF, Equivalent


Part Number

SN74AUC2G32

Description

DUAL 2-INPUT POSITIVE-OR GATE

Manufacture

etcTI

Total Page 17 Pages
Datasheet
Download SN74AUC2G32 Datasheet


SN74AUC2G32
www.ti.com
SN74AUC2G32
DUAL 2-INPUT POSITIVE-OR GATE
SCES478C – AUGUST 2003 – REVISED JANUARY 2007
FEATURES
Available in the Texas Instruments
NanoFree™ Package
Optimized for 1.8-V Operation and is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub-1-V Operable
Max tpd of 1.5 ns at 1.8 V
Low Power Consumption, 10 µA at 1.8 V
• ±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DCT PACKAGE
(TOP VIEW)
1A 1
1B 2
2Y 3
8 VCC
7 1Y
6 2B
1A
1B
2Y
GND
DCU PACKAGE
(TOP VIEW)
18
27
36
45
VCC
1Y
2B
2A
YZP PACKAGE
(BOTTOM VIEW)
GND 4 5 2A
2Y 3 6 2B
1B 2 7 1Y
1A 1 8 VCC
GND
4
5 2A
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This dual 2-input positive-OR gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to
1.95-V VCC operation.
The SN74AUC2G32 performs the Boolean function Y = A + B or Y = A × B in positive logic.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
For more information about AUC Little Logic devices, please refer to the TI application report, Applications of
Texas Instruments AUC Sub-1-V Little Logic Devices, literature number SCEA027.
ORDERING INFORMATION
TA
–40°C to 85°C
PACKAGE (1)
NanoFree – WCSP (DSBGA)
0.23-mm Large Bump – YZP
(Pb-free)
SSOP – DCT
ORDERABLE PART NUMBER
Reel of 3000 SN74AUC2G32YZPR
Reel of 3000 SN74AUC2G32DCTR
VSSOP – DCU
Reel of 3000 SN74AUC2G32DCUR
TOP-SIDE MARKING(2)
_ _ _UG_
U32_ _ _
U32_
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2007, Texas Instruments Incorporated

SN74AUC2G32
SN74AUC2G32
DUAL 2-INPUT POSITIVE-OR GATE
SCES478C – AUGUST 2003 – REVISED JANUARY 2007
FUNCTION TABLE
(each gate)
INPUTS
AB
HX
XH
LL
OUTPUT
Y
H
H
L
LOGIC DIAGRAM (POSITIVE LOGIC)
1
1A
2
1B
7
1Y
5
2A
6
2B
3
2Y
www.ti.com
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
VCC Supply voltage range
VI Input voltage range(2)
VO Voltage range applied to any output in the high-impedance or power-off state(2)
VO Output voltage range(2)
IIK Input clamp current
VI < 0
IOK Output clamp current
VO < 0
IO Continuous output current
Continuous current through VCC or GND
θJA Package thermal impedance(3)
DCT package
θJA Package thermal impedance(3)
DCU package
θJA Package thermal impedance(3)
YZP package
Tstg Storage temperature range
MIN MAX UNIT
–0.5 3.6 V
–0.5 3.6 V
–0.5 3.6 V
–0.5
VCC + 0.5
–50
V
mA
–50 mA mA
±20 mA
±100 mA
220 °C/W
227 °C/W
102 °C/W
–65 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
2 Submit Documentation Feedback


Features www.ti.com SN74AUC2G32 DUAL 2-INPUT POS ITIVE-OR GATE SCES478C – AUGUST 2003 – REVISED JANUARY 2007 FEATURES • Available in the Texas Instruments Nan oFree™ Package • Optimized for 1.8- V Operation and is 3.6-V I/O Tolerant t o Support Mixed-Mode Signal Operation Ioff Supports Partial-Power-Down Mod e Operation • Sub-1-V Operable • Ma x tpd of 1.5 ns at 1.8 V • Low Power Consumption, 10 µA at 1.8 V • ±8-m A Output Drive at 1.8 V • Latch-Up Pe rformance Exceeds 100 mA Per JESD 78, C lass II • ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A ) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) DCT PACKAGE (TOP VIEW) 1A 1 1B 2 2Y 3 8 VCC 7 1Y 6 2B 1A 1B 2Y GND DCU PACKAG E (TOP VIEW) 18 27 36 45 VCC 1Y 2B 2A YZP PACKAGE (BOTTOM VIEW) GND 4 5 2A 2 Y 3 6 2B 1B 2 7 1Y 1A 1 8 VCC GND 4 5 2A See mechanical drawings for dimen sions. DESCRIPTION/ORDERING INFORMATIO N This dual 2-input positive-OR gate is operational at 0.8-V to 2.7-V VCC, but is designed spec.
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