SN74AUC2G34 GATE Datasheet

SN74AUC2G34 Datasheet, PDF, Equivalent


Part Number

SN74AUC2G34

Description

DUAL BUFFER GATE

Manufacture

etcTI

Total Page 21 Pages
Datasheet
Download SN74AUC2G34 Datasheet


SN74AUC2G34
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SN74AUC2G34
DUAL BUFFER GATE
SCES514B – NOVEMBER 2003 – REVISED JANUARY 2007
FEATURES
Available in the Texas Instruments
NanoFree™ Package
Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal
Operation
Ioff Supports Partial-Power-Down Mode
Operation
Sub-1-V Operable
Max tpd of 1.6 ns at 1.8 V
Low Power Consumption, 10 µA at 1.8 V
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
DRL PACKAGE
(TOP VIEW)
YZP PACKAGE
(BOTTOM VIEW)
1A
1
6
1Y
1A 1 6 1Y
1A 1
6 1Y
2A 3 4 2Y
GND 2 5 V
GND 2
5V
GND 2
CC
5V
CC
CC
1A 1 6 1Y
GND
2
5
V 2A 3 4 2Y
CC 2A 3 4 2Y
2A 3 4 2Y
DESCRIPTION/ORDERING INFORMATION
This dual buffer gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC
operation.
The SN74AUC2G34 performs the Boolean function Y = A in positive logic.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the
package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
TA
–40°C to 85°C
ORDERING INFORMATION
PACKAGE (1)
ORDERABLE PART NUMBER TOP-SIDE MARKING(2)
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
Reel of 3000 SN74AUC2G34YZPR
_ _ _U9_
SOT-563 – DRL
Reel of 4000 SN74AUC2G34DRLR
U9_
SOT-23 – DBV
Reel of 3000 SN74AUC2G34DBVR
U34_
SC-70 – DCK
Reel of 3000 SN74AUC2G34DCKR
U9_
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2007, Texas Instruments Incorporated

SN74AUC2G34
SN74AUC2G34
DUAL BUFFER GATE
SCES514B – NOVEMBER 2003 – REVISED JANUARY 2007
FUNCTION TABLE
(EACH GATE)
INPUT
A
H
L
OUTPUT
Y
H
L
LOGIC DIAGRAM (POSITIVE LOGIC)
1A 1
6 1Y
2A 3
4 2Y
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Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
VCC Supply voltage range
VI Input voltage range(2)
VO Voltage range applied to any output in the high-impedance or power-off state(2)
VO Output voltage range(2)
IIK Input clamp current
VI < 0
IOK Output clamp current
VO < 0
IO Continuous output current
Continuous current through VCC or GND
DBV package
θJA Package thermal impedance(3)
DCK package
DRL package
YZP package
Tstg Storage temperature range
MIN MAX UNIT
–0.5 3.6 V
–0.5 4.1 V
–0.5 4.1 V
–0.5
VCC + 0.5
–50
V
mA
–50 mA
±20 mA
±100 mA
165
259
°C/W
142
123
–65 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
2 Submit Documentation Feedback


Features www.ti.com SN74AUC2G34 DUAL BUFFER GATE SCES514B – NOVEMBER 2003 – REVISED JANUARY 2007 FEATURES • Available in the Texas Instruments NanoFree™ Pa ckage • Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support M ixed-Mode Signal Operation • Ioff Sup ports Partial-Power-Down Mode Operation • Sub-1-V Operable • Max tpd of 1. 6 ns at 1.8 V • Low Power Consumptio n, 10 µA at 1.8 V • ±8-mA Output Dr ive at 1.8 V • Latch-Up Performance E xceeds 100 mA Per JESD 78, Class II • ESD Protection Exceeds JESD 22 – 200 0-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Char ged-Device Model (C101) DBV PACKAGE (T OP VIEW) DCK PACKAGE (TOP VIEW) DRL P ACKAGE (TOP VIEW) YZP PACKAGE (BOTTOM VIEW) 1A 1 6 1Y 1A 1 6 1Y 1A 1 6 1Y 2A 3 4 2Y GND 2 5 V GND 2 5V GN D 2 CC 5V CC CC 1A 1 6 1Y GND 2 5 V 2A 3 4 2Y CC 2A 3 4 2Y 2A 3 4 2Y DESCRIPTION/ORDERING INFORMATION This d ual buffer gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V t.
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