SN74AUC2G04 GATE Datasheet

SN74AUC2G04 Datasheet, PDF, Equivalent


Part Number

SN74AUC2G04

Description

DUAL INVERTER GATE

Manufacture

etcTI

Total Page 18 Pages
Datasheet
Download SN74AUC2G04 Datasheet


SN74AUC2G04
SN74AUC2G04
DUAL INVERTER GATE
D Available in the Texas Instruments
NanoStarand NanoFreePackages
D Optimized for 1.8-V Operation and Is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
D Ioff Supports Partial-Power-Down Mode
Operation
D Sub 1-V Operable
D Max tpd of 1.7 ns at 1.8 V
D Low Power Consumption, 10 µA at 1.8 V
D ±8-mA Output Drive at 1.8 V
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
SCES437A – APRIL 2003 – REVISED JUNE 2003
DBV OR DCK PACKAGE
(TOP VIEW)
1A
GND
2A
1
2
3
6 1Y
5 VCC
4 2Y
YEP OR YZP PACKAGE
(BOTTOM VIEW)
2A 3 4 2Y
GND 2 5 VCC
1A 1 6 1Y
description/ordering information
This dual inverter is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC
operation.
The SN74AUC2G04 performs the Boolean function Y = A.
NanoStarand NanoFreepackage technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
TA
PACKAGE†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING‡
–40°C to 85°C
NanoStar– WCSP (DSBGA)
0.23-mm Large Bump – YEP
NanoFree– WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
Tape and reel SN74AUC2G04YEPR
Tape and reel SN74AUC2G04YZPR
_ _ _UC_
SOT (SOT-23) – DBV
Tape and reel SN74AUC2G04DBVR U04_
SOT (SC-70) – DCK
Tape and reel SN74AUC2G04DCKR UC_
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 2003, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1

SN74AUC2G04
SN74AUC2G04
DUAL INVERTER GATE
SCES437A – APRIL 2003 – REVISED JUNE 2003
FUNCTION TABLE
(each inverter)
INPUT OUTPUT
AY
HL
LH
logic diagram (positive logic)
1
1A
6
1Y
3
2A
4
2Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Voltage range applied to any output in the high-impedance or power-off state, VO
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 3.6 V
Output voltage range, VO (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V
Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, IOK (VO < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, IO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
Package thermal impedance, θJA (see Note 2): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165°C/W
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258°C/W
YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 123°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265


Features SN74AUC2G04 DUAL INVERTER GATE D Availa ble in the Texas Instruments NanoStar and NanoFree Packages D Optimized for 1.8-V Operation and Is 3.6-V I/O To lerant to Support Mixed-Mode Signal Ope ration D Ioff Supports Partial-Power-Do wn Mode Operation D Sub 1-V Operable D Max tpd of 1.7 ns at 1.8 V D Low Power Consumption, 10 µA at 1.8 V D ±8-mA O utput Drive at 1.8 V D Latch-Up Perform ance Exceeds 100 mA Per JESD 78, Class II D ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 2 00-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) SCES437A APRIL 2003 – REVISED JUNE 2003 DBV OR DCK PACKAGE (TOP VIEW) 1A GND 2A 1 2 3 6 1Y 5 VCC 4 2Y YEP OR YZP PACK AGE (BOTTOM VIEW) 2A 3 4 2Y GND 2 5 VCC 1A 1 6 1Y description/ordering inform ation This dual inverter is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. The SN74AUC2G04 performs the Boolean function Y = A. NanoStar and NanoFree package technology is a major .
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